ST10F280 STMicroelectronics, ST10F280 Datasheet
ST10F280
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... REGULATOR FOR 3.3 V CORE SUPPLY). TEMPERATURE RANGE: -40 +125 GENERAL PURPOSE P4.5 CAN1_RxD P4.6 CAN1_TxD P4.4 CAN2_RxD P4.7 CAN2_TxD ST10F280 PRODUCT PREVIEW PBGA208 ( 1.96 - Pitch 1.27 mm) (Plastic Bold Grid Array) ORDER CODE: ST10F280-JT3 ° 512K Byte Flash Memory CPU-Core and MAC Unit 16 16K Byte PEC XRAM 16 ...
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... ST10F280 TABLE OF CONTENTS 1 - INTRODUCTION ........................................................................................................ 2 - BALL DATA ............................................................................................................... 3 - FUNCTIONAL DESCRIPTION ................................................................................... 4 - MEMORY ORGANIZATION ....................................................................................... 5 - INTERNAL FLASH MEMORY ................................................................................... 5.1 - OVERVIEW ................................................................................................................ 5.2 - OPERATIONAL OVERVIEW ...................................................................................... 5.3 - ARCHITECTURAL DESCRIPTION ............................................................................ 5.3.1 - Read Mode ................................................................................................................. 5.3.2 - Command Mode ......................................................................................................... 5.3.3 - Flash Status Register ................................................................................................. 5.3.4 - Flash Protection Register ........................................................................................... 5.3.5 - Instructions Description .............................................................................................. 5.3.6 - Reset Processing and Initial State .............................................................................. ...
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... Alternate Functions of PORT1 .................................................................................... 12.4 - PORT 2 ....................................................................................................................... 12.4.1 - Alternate Functions of Port 2 ..................................................................................... 12.5 - PORT 3 ....................................................................................................................... 12.5.1 - Alternate Functions of Port 3 ...................................................................................... 12.6 - PORT 4 ....................................................................................................................... 12.6.1 - Alternate Functions of Port 4 ...................................................................................... 12.7 - PORT 5 ....................................................................................................................... 12.7.1 - Port 5 Schmitt Trigger Analog Inputs .......................................................................... 12.8 - PORT 6 ....................................................................................................................... 12.8.1 - Alternate Functions of Port 6 ...................................................................................... 12.9 - PORT 7 ....................................................................................................................... 12.9.1 - Alternate Functions of Port 7 ...................................................................................... ST10F280 ...
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... ST10F280 12.10 - PORT 8 ....................................................................................................................... 12.10.1 - Alternate Functions of Port 8 ...................................................................................... 12.11 - XPORT 9 .................................................................................................................... 12.12 - XPORT 10 .................................................................................................................. 12.12.1 - Alternate Functions of XPort 10 .................................................................................. 12.12.2 - New Disturb Protection on Analog Inputs ................................................................... 13 - A/D CONVERTER ...................................................................................................... 13.1 - A/D CONVERTER MODULE ...................................................................................... 13.2 - MULTIPLEXAGE OF TWO BLOCKS OF 16 ANALOG INPUTS ................................ 13.3 - XTIMER PERIPHERAL (TRIGGER FOR ADC CHANNEL INJECTION) ................... ...
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... CLKOUT and READY ................................................................................................. 20.4.13 - External Bus Arbitration .............................................................................................. 20.4.14 - High-Speed Synchronous Serial Interface (SSC) Timing ........................................... 20.4.14.1 Master Mode................................................................................................................ 20.4.14.2 Slave mode.................................................................................................................. 21 - PACKAGE MECHANICAL DATA 22 - ORDERING INFORMATION ...................................................................................... ....................................................................................................... ........................................................................... ST10F280 131 131 131 132 135 135 135 136 136 139 148 149 155 155 155 ...
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... ST10F280 1 - INTRODUCTION The ST10F280 is a new derivative of the Microelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance ( million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides on-chip high-speed single voltage on-chip high-speed RAM, and clock generation via PLL ...
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... BALL DATA The ST10F280 package is a PBGA 1.96 mm. The pitch of the balls is 1.27 mm. The signal assignment of the 208 balls is described in Figure 2 for the configuration and in Table 1 for the ball signal assignment. This package has 25 additional thermal balls. Figure 2 : Ball Configuration (bottom view) ...
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... ST10F280 Table 1 : Ball Description Ball Symbol Type Number P6.0 – P6.7 I P8.0 – P8.7 I/O E2 I/O F3 I/O F2 I/O G3 I/O G2 I/O H4 I/O H3 I/O H2 I/O P7.0 – P7.7 I I/O K3 I/O K4 I/O L2 I/O 8/186 Port 8-bit bidirectional I/O port bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state ...
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... GPT2 Timer T6 External Up / Down Control Input P5.11 T5EUD GPT2 Timer T5 External Up / Down Control Input P5.12 T6IN GPT2 Timer T6 Count Input P5.13 T5IN GPT2 Timer T5 Count Input P5.14 T4EUD GPT1 Timer T4 External Up / Down Control Input P5.15 T2EUD GPT1 Timer T2 External Up / Down Control Input ST10F280 Function 9/186 ...
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... ST10F280 Table 1 : Ball Description (continued) Ball Symbol Type Number P2.0 – P2.15 I/O T7 I/O P8 I/O R8 I/O T8 I/O T9 I/O P9 I/O R9 I/O U9 I/O T10 I/O I R10 I/O I P10 I/O I T11 I/O I R11 I/O I U12 I/O I P11 I/O I T12 I 10/186 Port 16-bit bidirectional I/O port bit-wise programmable for input or output via direction bits ...
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... CAN2_RxD CAN2 Receive Data Input P4.5 A21 Segment Address Line CAN1_RxD CAN1 Receive Data Input P4.6 A22 Segment Address Line, CAN_TxD CAN1_TxD CAN1 Transmit Data Output P4.7 A23 Most Significant Segment Address Line CAN2_TxD CAN2 Transmit Data Output ST10F280 Function 11/186 ...
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... External Access Enable pin. A low level at this pin during and after Reset forces the ST10F280 to begin instruction execution out of external memory. A high level forces execution out of the internal Flash Memory. PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H bit-wise programmable for input or output via direction bits ...
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... For a pin configured as input, the output driver is put into high-impedance state. XPort 9 outputs can be configured as push/pull or open drain drivers. XPORT9.0 XPORT9.1 XPORT9.2 XPORT9.3 XPORT9.4 XPORT9.5 XPORT9.6 XPORT9.7 XPORT9.8 XPORT9.9 XPORT9.10 XPORT9.11 XPORT9.12 XPORT9.13 XPORT9.14 XPORT9.15 ST10F280 Function 13/186 ...
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... NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F280 to go into power down mode. If NMI is high and PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal mode ...
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... Decoupling pin: a decoupling capacitor of ~330 nF must be connected between this pin and nearest V SS 3.3V Decoupling pin: a decoupling capacitor of ~330 nF must be connected between this pin and V nearest pin. SS Digital Supply Voltage during normal operation, idle mode and power down mode ST10F280 Function pin. 15/186 ...
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... ST10F280 Table 1 : Ball Description (continued) Ball Symbol Type Number A11 A13 A16 A17 B17 F17 G4 H1 K16 K17 L1 L4 N15 N17 R17 T15 T16 U7 U10 U13 U14 U16 U17 16/186 Digital Ground. Function ...
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... FUNCTIONAL DESCRIPTION The architecture of the ST10F280 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The Figure 3 : Block Diagram 512K Byte Flash Memory 16K Byte XRAM P4.5 CAN1_RxD CAN1 P4.6 CAN1_TxD P4.4 CAN2_RxD CAN2 P4.7 CAN2_TxD Port 6 8 XPORT10 ...
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... BUSCONx register corresponding to address matching ADDRSELx register As the XRAM appears like external memory, it cannot be used for the ST10F280’s system stack or register banks. The XRAM is not provided for single bit storage and therefore is not bit address- able. ...
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... Figure 4 : ST10F280 On-chip Memory Mapping Data Page Number * Blocks 0, 1 and 2 may be remapped from segment 0 to segment 1 by setting SYSCON-ROMS1 (before EINIT) Data Page Number and Absolute Memory Address are hexadecimal values. 09’0000 Block10 = 64K Bytes 08’0000 05’0000 Block6 = 64K Bytes 04’ ...
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... ST10F280 XPERCON (F024h / 12h Bit CAN1EN CAN1 Enable Bit 0 Accesses to the on-chip CAN1 XPeripheral and its functions are disabled. P4.5 and P4.6 pins can be used as general purpose I/Os. Address range 00’EF00h-00’EFFFh is only directed to external memory if CAN2EN and XPWM bits are cleared also. ...
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... CPU frequency up to 40MHz. Instruction fetches and data operand reads are performed with all addressing modes of the ST10F280 instruction set. In order to optimize the programming time of the internal Flash, blocks of 8K Bytes, 16K Bytes, 32K Bytes, 64K Bytes can be used. But the size of the blocks does not apply to the whole memory space, see details in Table 2 ...
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... ST10F280 Instructions and Commands All operations besides normal read operations are initiated and controlled by command sequences written to the Flash Command Interface (CI). The Command Interface (CI) interprets words written to the Flash memory and enables one of the following operations: – Read memory array – Program Word – ...
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... FSB.2, or Error on FSB.5 and Erase Timeout on FSB.3 bit. Any read attempt in Flash during EPC operation will automatically output these five bits. The EPC sets bit FSB.2, FSB.3, FSB.5, FSB.6 and FSB.7. Other bit are reserved for future use and should be masked. ST10F280 the program-Erase Controller 23/186 ...
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... ST10F280 Flash Status (see note for address FSB.7 Flash Status bit 7: Data Polling Bit Programming Operation: this bit outputs the complement of the bit 7 of the word being programmed, and after completion, will output the bit 7 of the word programmed. Erasing Operation: outputs a ‘0’ during erasing, and ‘1’ after erasing completion. ...
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... FSB.3 is ‘1’, the timeout has expired and the EPC is erasing the block(s). If the second command given is not an erase con- firm or if the coded cycles are wrong, the instruc- tion aborts, and the device is reset to Read Mode. ST10F280 ...
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... ST10F280 It is not necessary to program the block with 0000h as the EPC will do this automatically before the erasing to FFFFh. Read operations after the EPC has started, output the Flash Status Regis- ter. During the execution of the erase by the EPC, the device accepts only the Erase Suspend and Read/Reset instructions. Data Polling bit FSB.7 returns ‘ ...
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... Note that Code Temporary Unprotection instruction must be used when it is necessary to modify the Flash with protected code (SCP), since the write/erase routines must be executed from a memory external to Flash space. Usually, the write/erase routines, executed in RAM, ends with a return to Flash space where a CTP instruction restore the protection. ST10F280 27/186 ...
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... ST10F280 Table 3 : Instructions Instruction Mne Cycle Read/Reset RD 1+ Read/Reset RD 3+ Program Word PW 4 Block Erase BE 6 Chip Erase CE 6 Erase Suspend ES 1 Erase Resume ER 1 Set Block/Code Protection SP 4 Read Protection Status RP 4 Block Temporary BTU 4 Unprotection Code Temporary CTU 1 Unprotection ...
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... Flash Memory Configuration The default memory configuration ST10F280 Memory is determined by the state of the EA pin at reset. This value is stored in the Internal ROM Enable bit (named ROMEN) of the SYSCON register. When ROMEN = 0, the internal Flash is disabled and external ROM is used for startup control. ...
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... ST10F280 5.5.2 - Basic Flash Access Control When accessing the Flash all command write addresses have to be located within the active Flash memory space. The active Flash memory space is that logical address range which is covered by the Flash after mapping. When using data page pointer (DPP) for addressing the Flash, make sure that address bit A15 and A14 of the command addresses are reflected in both LSBs of the selected data page pointer (A15 DPPx ...
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... R6 with command address ;(used in command cycle 2) ;push data page pointer 0 and load it to point to ;segment 2 ;load register R7 with 1st CI enable command ;command cycle 1 ;load register R7 with 2cd CI enable command ;command cycle 2 ;load register R7 with Program Word command ;command cycle 3 ST10F280 31/186 ...
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... ST10F280 POP DPP0 EXTS R11, #1 MOV [R12], R13 Data_Polling: EXTS R11, #1 MOV R7, [R12] MOV R6, R7 XOR R7, R13 JNB R7.7, Prog_OK JNB R6.5, Data_Polling EXTS R11, #1 MOV R7, [R12] XOR R7, R13 JNB R7.7, Prog_OK Prog_Error: MOV R7, #0F0h EXTS R11, #1 MOV [R12], R7 ... ... ...
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... R7 with Read/Reset command ;use EXTended addressing for next MOV instruction ;address is don’t care for Read/Reset command ;here place specific Error handling code ;When erasing operation finished succesfully, ;Flash is set back automatically to normal Read Mode ST10F280 33/186 ...
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... Boot-ROM. No part of the standard mask Memory or Flash Memory area is required for this. After entering BSL mode and the respective initialization the ST10F280 scans the RxD0 line to receive a zero Byte, one start Bit, eight ‘0’ data Bits and one stop Bit. ...
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... When the ST10F280 has entered BSL mode, the following configuration is automatically set (values that deviate from the normal reset values, are marked ): Watchdog Timer: Disabled Context Pointer CP: FA00h Stack Pointer SP: FA40h Register S0CON: 8011h Register S0BG: Acc. to ‘00’ Byte In this case, the watchdog timer is disabled, so the bootstrap loading sequence is not time limited ...
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... BSL mode must be terminated first. The ST10F280 exits BSL mode upon a software reset (ignores the level on P0L. hardware reset that adds a (P0L.4 must be high). After a reset the ST10F280 will start executing from location 00’0000h of the internal Flash or the external memory, as programmed via pin EA. the system ...
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... The calculation of the serial Baud rate for ASC0 from the length of the first zero Byte that is received, allows the operation of the bootstrap loader of the ST10F280 with a wide range of Baud rates. However, the upper and lower limits have to be kept, in order to insure proper data transfer. ...
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... SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10F280’s instructions can be exe- cuted in one instruction cycle which requires 50ns at 40MHz CPU clock. For example, shift and rotate instructions are processed in one instruc- tion cycle independent of the number of bits to be shifted ...
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... The co-processor instructions extend the ST10 CPU instruction set with multiply, multiply-accu- mulate, 32-bit signed arithmetic operations. A new transfer instruction CoMOV has also been added to take benefit of the new addressing capa- bilities. ST10F280 Reset Value: 0xx0h ...
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... ST10F280 6.1.1 - Features 6.1.1.1 - Enhanced Addressing Capabilities – New addressing modes including a double indi- rect addressing mode with pointer post-modifi- cation. – Parallel Data Move : this mechanism allows one operand move during Multiply-Accumulate in- structions without penalty. – New tranfer instructions CoSTORE (for fast ac- cess to the MAC SFRs) and CoMOV (for fast memory to memory table transfer) ...
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... Instruction Set Summary The Table 4 lists the instructions of the ST10F280. The various addressing modes, instruction operation, parameters for conditional execution of instructions, opcodes and a detailed description of each instruc- tion can be found in the “ST10 Family Programming Manual”. Table 4 : Instruction Set Summary ...
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... ST10F280 Table 4 : Instruction Set Summary Mnemonic JNBS Jump relative and set bit if direct bit is not set CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met CALLS Call absolute subroutine in any code segment PCALL Push direct word register onto system stack and call absolute subroutine ...
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... CoMACRu CoMACRus CoMACRsu CoMACR, rnd CoMACRu, rnd CoMACRus, rnd CoMACRsu, rnd CoNOP CoNEG CoNEG, rnd CoRND CoSTORE CoMOV Addressing Modes [IDX ], [ [ [IDX ], [ [ [IDX ], [ [ [Rw m [IDX ] i [IDX ], [ CoReg n [Rw , Coreg n [IDX ], [ ST10F280 Repeatability Yes Yes Yes Yes Yes No No Yes Yes 43/186 ...
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... ST10F280 Mnemonic CoMACM CoMACMu CoMACMus CoMACMsu CoMACM- CoMACMu- CoMACMus- CoMACMsu- CoMACM, rnd CoMACMu, rnd CoMACMus, rnd CoMACMsu, rnd CoMACMR CoMACMRu CoMACMRus CoMACMRsu CoMACMR, rnd CoMACMRu, rnd CoMACMRus, rnd CoMACMRsu, rnd CoADD CoADD2 CoSUB CoSUB2 CoSUBR CoSUB2R CoMAX CoMIN CoLOAD CoLOAD- CoLOAD2 ...
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... QX ] (IDX ) (IDX ) + ( (IDX ) (IDX ) ( (Rwn) (Rwn) (no-op) (Rwn) (Rwn) +2 (n=0-15) (Rwn) (Rwn)2 (k=0-15) ] (Rwn) (Rwn (Rwn) (Rwn) (QR j Description ST10F280 Address Pointer Operation ) (i, j =0, (i, j =0, (n=0-15;j =0, (n=0-15; j =0,1) j Address in Opcode 00000b 00001b 00010b 00100b 00101b 00110b 45/186 ...
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... RDYPOL in the associated BUSCON register. 7.1 - Programmable Chip Select Timing Control The ST10F280 allows the user to adjust the posi- tion of the CSx lines changes. By default (after reset), the CSx lines are changing half a CPU clock cycle (12 ...
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... BUS ALE - BTYP ACT0 CTL0 SFR BUS ALE - BTYP ACT1 CTL1 SFR BUS ALE - BTYP ACT2 CTL2 ST10F280 Bus Cycle Data Data Read/Write Delay Reset Value: 0xx0h MTT RWD MCTC Reset Value: 0000h MTT RWD MCTC Reset Value: 0000h MTT ...
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... ST10F280 BUSCON3 (FF18h / 8Ch CSW CSR RDY RDY - EN3 EN3 POL3 EN3 BUSCON4 (FF1Ah / 8Dh CSW CSR RDY RDY - EN4 EN4 POL4 EN4 Bit RDYPOLx Ready Active Level Control 0 The active level on the READY pin is low, bus cycle terminates with a ‘0’ on READY pin, 1 The active level on the READY pin is high, bus cycle terminates with a ‘ ...
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... When this counter reaches zero, a standard interrupt is performed corresponding source related vector location. PEC services are very well suited to perform the transmission or the reception of blocks of data. The ST10F280 has 8 PEC channels, each of them offers such fast interrupt-driven data transfer capabilities. EXISEL (F1DAh / EDh ...
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... Interrupt on any edge (rising or falling) Always enter Power Down mode, exit if EXxIN level changed. 8.2 - Interrupt Registers and Vectors Location List Table 7 shows all the available ST10F280 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Table 7 : Interrupt Sources ...
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... S0RINT 00’00ACh S0EINT 00’00B0h SCTINT 00’00B4h SCRINT 00’00B8h SCEINT 00’00BCh PWMINT 00’00FCh XP0INT 00’0100h XP1INT 00’0104h XP2INT 00’0108h XP3INT 00’010Ch ST10F280 Trap Number 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 44h 45h 46h 20h 21h 3Dh 3Eh 22h 23h 24h ...
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... ST10F280 Hardware traps are exceptions or error conditions that arise during run-time. They cause immediate non-maskable system reaction similar to a standard interrupt service dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any other program execution ...
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... STOTRAP 00’0010h STUTRAP 00’0018h BTRAP 00’0028h BTRAP 00’0028h BTRAP 00’0028h BTRAP 00’0028h BTRAP 00’0028h BTRAP 00’0028h [2Ch –3Ch] Any [00’0000h– 00’01FCh] in steps of 4h ST10F280 Trap * Trap Number Priority MAXIMUM 00h III 00h III 00h III 02h II 04h II 06h II 0Ah I 0Ah ...
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... ST10F280 9 - CAPTURE/COMPARE (CAPCOM) UNITS The ST10F280 has two 16 channels CAPCOM units as described in Figure 12. These support generation and control of timing sequences channels with a maximum resolution of 200ns at 40MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse ...
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... The numbers for the timer periods are based on a reload value of 0000h. Note that some numbers may be rounded to 3 significant figures. TxIR TxIR of the five compare , for the timer input Tx clocks. The timer input ST10F280 Interrupt Request Interrupt Request modes are frequencies, 55/186 ...
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... ST10F280 Table 9 : Compare Modes Compare Modes Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated Mode 3 Pin set ‘ ...
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... Timer Input Selection T2I / T3I / T4I 001b 010b 011b 2.5MHz 1.25MHz 625kHz 400ns 0.8µs 1.6µs 26.2ms 52.4ms 104.8ms 100b 101b 110b 128 256 512 312.5kHz 156.25kHz 78.125kHz 3.2µs 6.4µs 12.8µs 209.7ms 419.4ms 838.9ms ST10F280 111b 1024 39.1kHz 25.6µs 1.678s 57/186 ...
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... ST10F280 Figure 15 : Block Diagram of GPT1 T2EUD CPU Clock n 2 n=3...10 T2IN CPU Clock n 2 n=3...10 T3IN T3EUD T4IN CPU Clock n 2 n=3...10 T4EUD 10.2 - GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both ...
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... T5EUD CPU Clock n 2 n=2...9 T5IN CAPIN T6IN CPU Clock n 2 n=2...9 T6EUD U/D T5 GPT2 Timer T5 Mode Control Clear Capture GPT2 CAPREL T6 GPT2 Timer T6 Mode Control U/D ST10F280 Interrupt Request Interrupt Request Reload Interrupt Request Toggle FF T60TL T6OUT to CAPCOM Timers 59/186 ...
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... ST10F280 11 - PWM MODULE 11.1 - Standard PWM Module The pulse width modulation module can generate up to four PWM output signals using edge-aligned or centre-aligned PWM. In addition, the PWM module can generate PWM burst signals and Figure 17 : Block Diagram of PWM Module Clock 1 Input Control ...
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... New PWM Module : XPWM The new Pulse Width Modulation (XPWM) Module of the ST10F280 is mapped on the XBUS inter- face (Address range 00’EC00h-00’ECFFh) and allows the generation independent PWM signals.The XPWM is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the new XPERCON register ...
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... ST10F280 11.2.1 - Operating Modes The XPWM module provides four different operat- ing modes: – Mode 0 Standard PWM generation (edge aligned PWM) available on all four channels – Mode 1 Symmetrical PWM generation (center aligned PWM) available on all four channels – Burst mode combines channels 0 and 1 – ...
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... This mode is referred to as Center Aligned PWM, because the value in the pulse width (shadow) register effects both edges of the output signal symmetrically Change Count Direction PWM_Period = 2 * ([XPPx Mode1 Duty Cycle 100% 87.5% 75% 50% 25% 12.5% 0% LSR ST10F280 63/186 ...
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... ST10F280 11.2.1.3 - Burst Mode Burst mode is selected by setting bit PB01 in reg- ister XPWMCON1 to ‘1’. This mode combines the signals from XPWM channels 0 and 1 onto the port pin of channel 0. The output of channel 0 is replaced with the logical AND of channels 0 and 1. The output of channel 1 can still be used at its associated output pin (if enabled) ...
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... LSR PTRx Reset by Hardware PTx stopped Retrigger after Pulse has started : Write PWx value to PTx Set PTRx by Software for Next Pulse Trigger before Pulse has started : Write PWx value to PTx; Shortens Delay Time t D ST10F280 7 LSR 7 65/186 ...
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... ST10F280 11.2.2 - XPWM Module Registers The XPWM module is controlled via two sets of registers. The waveforms are selected by the channel specific registers XPTx (timer), XPPx (period) and XPWx (pulse width). Three common registers control the operating modes and the general functions (XPWMCON0 and XPWMCON1) of the PWM module as well as the interrupt behavior (XP2IC) ...
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... Channel x works in respective standard mode 1 Channel x operates in single shot mode PIE2 PIE1 PIE0 PTI3 PTI2 Function CPU / 64 CPU PM3 PM2 - - - RW RW Function ST10F280 Reset Value: 0000h PTI1 PTI0 PTR3 PTR2 PTR1 PTR0 Reset Value: 0000h PM1 PM0 PEN3 PEN2 PEN1 PEN0 RW 67/186 ...
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... ST10F280 11.2.3 - Interrupt Request Generation Each of the four channels of the XPWM module can generate an individual interrupt request. Each of these “channel interrupts” can activate the common “module interrupt”, which actually interrupts the CPU. This common module interrupt is controlled by the XPWM Module Interrupt Control register XP2IC( Xpe- ripherals 2 control register) ...
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... XPWx imme- diately sets the respective output, a XPTx value below the XPWx value clears the respective out- put. Note To prevent further PWM pulses from occurring intervention the respective counter must be stopped first. ST10F280 Reset Value: 0000h XPOLAR.3 XPOLAR.2 XPOLAR.1 XPOLAR ...
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... ST10F280 12 - PARALLEL PORTS In order to accept or generate single external con- trol signals or parallel data, the ST10F280 pro- vides up to 143 parallel I/O lines, organized into two 16-bit I/O port (Port 2, XPort9), eight 8-bit I/O ports (PORT0 made of P0H and P0L, PORT1 made of P1H and P1L, Port 4, Port 6, Port 7, Port 8) , one 15-bit I/O port (Port 3) and two 16-bit input port (Port 5, XPort10) ...
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... Figure 25 : SFRs Associated with the Parallel Ports ST10F280 71/186 ...
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... Y 12.1 - Introduction 12.1.1 - Open Drain Mode In the ST10F280 some ports provide Open Drain Control. This make is possible to switch the output driver of a port pin from a push/pull configuration to an open drain configuration. In push/pull mode a port output driver has an upper and a lower tran- sistor, thus it can actively drive the line either to a high or a low level ...
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... Input Threshold Control The standard inputs of the ST10F280 determine the status of input signals according to TTL levels. In order to accept and recognize noisy signals, CMOS-like input thresholds can be selected instead of the standard TTL thresholds for all pins of Port 2, Port 3, Port4, Port 7 and Port 8. These special thresholds are defined above the TTL thresholds and feature a defined hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds ...
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... ST10F280 For each feature, a 2-bit control field (ie. 4 bits) is provided for each group of 4 port pads (ie. a port nibble), in port output control registers POCONx. POCONx (F0yyh / zzh) for 8-bit Ports POCONx (F0yyh / zzh) for 16-bit Ports PN3DC PN3EC PN2DC RW RW Bit ...
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... In this case, the pin reflects the state of the port output latch. Thus, the alternate input function reads the value stored in the port output latch. This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch. ST10F280 Reset Value: 0000h ...
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... ST10F280 On most of the port lines, the user software is responsible for setting the proper direction when using an alternate input or output function of a pin. This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function. There are port lines, however, where the direction of the port line is switched automatically ...
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... Reset Value 00h A15 A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 8-bit 16-bit Multiplexed Bus Multiplexed Bus ST10F280 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 77/186 ...
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... ST10F280 When an external bus mode is enabled, the direc- tion of the port pin and the loading of data into the port output latch are controlled by the bus control- ler hardware. The input of the port output latch is disconnected from the internal bus and is switched to the line labeled “ ...
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... The input of the port output latch is disconnected from the internal bus and is switched to the line labeled “Alternate Data Out- put” via a multiplexer. The alternate data is the 16-bit intra-segment address. Reset Value 00h Reset Value 00h Reset Value 00h Reset Value 00h ST10F280 79/186 ...
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... ST10F280 While an external bus mode is enabled, the user software should not write to the port output latch, other- wise unpredictable results may occur. When the external bus modes are disabled, the contents of the direction register last written by the user becomes active. Figure 31 : PORT1 I/O and Alternate Functions Alternate Function P1H ...
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... Data Output”. When an overflow of the corresponding timer occurs, a '0' is written to the port output latch. In both cases, the output latch is clocked by the signal “Compare Trigger”. ST10F280 Reset Value: 0000h ...
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... ST10F280 The direction of the pin should be set to output by the user, otherwise the pin will be in the high-impedance state and will not reflect the state of the output latch. As can be seen from the port structure below, the user software always has free access to the port pin even when it is used as a compare output ...
Page 83
... Write DP2.y Direction Latch Read DP2.y 1 MUX Alternate Data 0 Output Write Port P2.y Compare Trigger Read P2.y Output Latch 1 1 MUX 0 Alternate Data Input Fast External Interrupt Input ST10F280 P2.y CCyIO Output EXxIN Buffer CPU Clock Input Latch x = 7... 15...0 83/186 ...
Page 84
... ST10F280 12.5 - Port 3 If this 15-bit port is used for general purpose I/O, the direction of each line can be configured by the cor- responding direction register DP3. Most port lines can be switched into push/pull or open drain mode by the open drain control register ODP3 (pins P3.15, P3.14 and P3.12 do not support open drain mode). ...
Page 85
... When the alternate output functions are not used, the “Alternate Data Output” line is in its inactive state, which is a high level ('1'). Port 3 pins with alternate output functions are: T6OUT, T3OUT, TxD0 and CLKOUT. ST10F280 WRH 85/186 ...
Page 86
... ST10F280 When the on-chip peripheral associated with a Port 3 pin is configured to use both the alternate input and output function, the descriptions above apply to the respective current operating mode. The direction must be set accordingly. Port 3 pins with alternate input/output functions are: MTSR, MRST, RxD0 and SCLK ...
Page 87
... Bit P4.y Port data register P4 bit y 1 “1” MUX 0 Alternate Function Enable Alternate Data 1 Output MUX 0 CPU Clock 1 MUX 0 SFR P4.7 P4 Function P3.12/BHE P3.15/CLKOUT Output Buffer Input Latch x = 15, 12 Reset Value 00h P4.5 P4.4 P4.3 P4 ST10F280 1 0 P4.1 P4 87/186 ...
Page 88
... ST10F280 DP4 (FFCAh / E5h Bit DP4.y Port direction register DP4 bit y DP4 Port line P4 input (high-impedance) DP4 Port line P4 output For CAN configuration support (see Chapter 15 - CAN Modules), Port 4 has a new open drain function, controlled with the new ODP4 register: ODP4 (F1CAh / E5h) ...
Page 89
... A17 A16 Segment Address Lines 1 “1” MUX 0 Alternate Function Enable Alternate Data 1 Output MUX 0 CPU Clock 1 MUX 0 ST10F280 b) CAN2_TxD CAN1_TxD CAN1_RxD CAN2_RxD p4.3 P4.2 P4.1 P4.0 Cans I/O and General Purpose Input / Output P4.y Output Buffer Input Latch y = 7...0 89/186 ...
Page 90
... ST10F280 Figure 40 : Block Diagram of P4.4 and P4.5 Pins Write DP4.x Direction Latch Read DP4.x Write P4.x Port Output Latch Read P4.x CANy.RxD XPERCON.a (CANyEN) XPERCON.b (CANzEN) 90/186 1 “1” MUX 0 “0” 1 MUX Alternate Function 0 Enable Alternate Data 1 Output MUX 0 1 MUX 0 & ...
Page 91
... CANy.TxD Data output XPERCON.a (CANyEN) XPERCON.b (CANzEN) "0" 1 "1" MUX 0 1 "0" MUX Alternate Function 0 Enable Alternate 1 Data Output MUX 0 1 MUX MUX MUX 0 1 "1" MUX MUX 0 1 MUX MUX 0 Output Buffer Clock Input Latch (CAN Channel ST10F280 P4.x 91/186 ...
Page 92
... ST10F280 12.7 - Port 5 This 16-bit input port can only read data. There is no output latch and no direction register. Data written to P5 will be lost. P5 (FFA2h / D1h P5.15 P5.14 P5.13 P5.12 P5.11 P5.10 P5 Bit P5.y Port data register P5 bit y (Read only) Alternate Functions of Port 5 Each line of Port 5 is also connected to one of the multiplexer of the Analog/Digital Converter ...
Page 93
... DP6.7 DP6.6 DP6.5 DP6.4 DP6.3 DP6.2 DP6.1 DP6 Analog Switch P5.y/ANy y = 15...0 Reset Value: 0000h P5DI P5DI P5DI P5DI DIS.5 DIS.4 DIS.3 DIS Reset Value 00h P6.5 P6.4 P6.3 P6 Reset Value 00h ST10F280 1 0 P5DI P5DI DIS.1 DIS P6.1 P6 93/186 ...
Page 94
... ST10F280 Bit DP6.y Port direction register DP6 bit y DP6 Port line P6 input (high-impedance) DP6 Port line P6 output ODP6 (F1CEh / E7h Bit ODP6.y Port 6 Open Drain control register bit y ODP6 Port line P6.y output driver in push/pull mode ODP6 Port line P6.y output driver in open drain mode 12 ...
Page 95
... DP7. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP7. 1 MUX MUX "0" "1" MUX 0 Alternate Function Enable Alternate * 1 Data Output MUX 0 1 MUX 0 ST10F280 P6.y Output Buffer CPU Clock Input Latch y = (0... 95/186 ...
Page 96
... ST10F280 P7 (FFD0h / E8h P7.y Port data register P7 bit y DP7 (FFD2h / E9h DP7.y Port direction register DP7 bit y DP7 Port line P7 input (high impedance) DP7 Port line P7 output ODP7 (F1D2h / E9h ODP7.y Port 7 Open Drain control register bit y ODP7 Port line P7.y output driver in push-pull mode ODP7 ...
Page 97
... Port Output Latch Read P7.y P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0 Alternate Function Alternate Data Output =1 Port Data Output EXOR CPU Clock 1 MUX 0 ST10F280 CC31IO CC30IO CC29IO CC28IO POUT3 POUT2 POUT1 POUT0 P7.y/POUTy Output Buffer y = 0...3 Input Latch 97/186 ...
Page 98
... ST10F280 Figure 48 : Block Diagram of Port 7 Pins P7.7...P7.4 Write ODP7.y Open Drain Latch Read ODP7.y Write DP7.y Direction Latch Read DP7.y 1 MUX Alternate 0 Data Output Write Port P7.y Compare Trigger Read P7.y 98/186 Output Latch 1 1 MUX 0 Alternate Latch Data Input ...
Page 99
... Capture input / compare output channel 23 SFR P8.7 P8 SFR DP8.7 DP8.6 DP8.5 DP8.4 DP8.3 DP8.2 DP8.1 DP8 ESFR ODP8.7 ODP8.6 ODP8.5 ODP8.4 ODP8.3 ODP8.2 ODP8.1 ODP8 Alternate Function ST10F280 Reset Value 00h P8.5 P8.4 P8.3 P8.2 P8 Reset Value 00h Reset Value 00h P8.0 ...
Page 100
... ST10F280 Figure 49 : Port 8 I/O and Alternate Functions Port 8 General Purpose Input / Output The port structures of Port 8 differ in the way the output latches are connected to the internal bus and to the pin driver (see the Figure 50). Pins P8.7...P8.0 (CC23IO...CC16IO) combine internal bus data and alternate data output before the port latch input the Port 2 pins ...
Page 101
... XP9SET XP9SET XP9SET . Function XP9CLR XP9CLR XP9CLR XP9CLR XP9CLR . Function XDP9 XDP9 XDP9 XDP9 XDP9 . Function ST10F280 Reset Value: 0000h XP9.5 XP9.4 XP9.3 XP9.2 XP9 Reset Value: 0000h XP9SET XP9SET XP9SET XP9SET XP9SET . Reset Value: 0000h XP9CLR XP9CLR XP9CLR XP9CLR XP9CLR . ...
Page 102
... ST10F280 XDP9SET (C202h XDP9 XDP9 XDP9 XDP9 XDP9 SET.15 SET.14 SET.13 SET.12 SET. Bit XDP9SET.y Writing a ‘1’ will set the corresponding bit in XDP9 register, Writing a ‘0’ has no effect. XDP9CLR (C204h XDP9 XDP9 XDP9 XDP9 XDP9 CLR.15 CLR.14 CLR.13 CLR.12 CLR ...
Page 103
... Function XP10.15 XP10.14 XP10.13 XP10.12 XP10.11 XP10.10 Alternate Function XP10.9 XP10.8 XP10.7 XP10.6 XP10.5 XP10.4 XP10.3 XP10.2 XP10.1 XP10.0 ST10F280 Reset Value: XXXXh XP10 XP10 XP10 XP10 XP10 . Alternate Function Analog Input AN16 Analog Input AN17 Analog Input AN18 Analog Input AN19 ...
Page 104
... ST10F280 12.12.2 - New Disturb Protection on Analog Inputs A new register is provided for additional disturb protection support on analog inputs for Port XP10: XP10DIDIS (C382h XP10 XP10 XP10 XP10 XP10 DIDIS DIDIS DIDIS DIDIS DIDIS .15 .14 .13 .12 . Bit XP10DIDIS.y XPort 10 Digital Disable register bit y 0 Port line XP10 ...
Page 105
... For applications which require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the ST10F280 supports four different conversion modes: Single channel conversion mode the analog level on a specified channel is sampled once and converted to a digital result ...
Page 106
... ST10F280 13.2 - Multiplexage of two blocks of 16 Analog Inputs The ADC can manage 16 analog inputs increase its capability, a new XADCMUX register is added to control the multiplexage between the first block of 16 channels on Port5 and the second block of 16 channels on XPort10. The conversion result register stays identical and only a software management can determine the block in use ...
Page 107
... Continue / stop modes – 4 memory mapped registers : • Control / prescaler • Start value • End value • Current value TUD TEN TCVR(n+ TCVR( TCVR(n)-1 1 TCVR(n)+1 x TSVR ST10F280 comments Timer disable Stop Decrement Decrement (Continue) Increment Increment (Continue) Load 107/186 ...
Page 108
... ST10F280 13.3.2 - Register Description 13.3.2.1 - TCR : Timer Control Register XTCR (C000h Bit TEN Timer Enable When TEN = ’0’, the Timer is disabled (reset value). To avoid glitches recommended to modify TCR in 2 steps, first with new values and and second by setting TEN. TUD Timer Up / Down Counting When TUD = ’ ...
Page 109
... XTCR : Control C002h XTSVR : Start Value C004h XTEVR : End Value C006h XTCVR : Current Value TSVR RW Function TEVR RW Function TCVR R Function Register Name Reset Value (Hexa) Reset Value: 0000h Reset Value: 0000h Reset Value: 0000h Access 0000h RW 0000h RW 0000h RW 0000h R ST10F280 109/186 ...
Page 110
... ST10F280 13.3.3 - Block Diagram Figure 53 : XTIMER Block Diagram XTCR ctl diff Timer output (XADCINJ) 13.3.3.1 - Clocks The XTCVR register clock is the prescaler output. The prescaler allows to divide the basic register frequency in order to offer a wide range of count- ing period, from 2**2 to 2**33 cycles (note that 1 cycle = 1 XCLK periods) ...
Page 111
... The XADCINJ output is the result of the (XTCVR = XTEVR) flag after differentiation. The duration of the output lasts two cycles (50ns at 40MHz). Figure 54 : XADCINJ Timer Output Figure 55 : External Connection for ADC Channel Injection CAPCOM2 XCLK XADCINJ 4 TCL =50ns Clock P7.7/CC31 Input UNIT Latch XTIMER XADCINJ ST10F280 Output trigger for ADC channel injection 111/186 ...
Page 112
... Asynchronous / Synchronous Serial Interface (ASCO) The asynchronous / synchronous serial interface (ASCO) provides serial communication between the ST10F280 and other microprocessors or external peripherals. A set of registers is used to configure and to control the ASCO serial interface: – P3, DP3, ODP3 for pin configuration ...
Page 113
... ST10F280 f CPU = (S0BRS)] x [(S0BRL CPU (S0BRS Async S0BRS = ‘1’ 40MHz CPU Reload Value Deviation Error (hexa) 0.0% / 0.0% 0000 / 0000 +6 ...
Page 114
... ST10F280 14.1.2 - ASCO in Synchronous Mode In synchronous mode, data are transmitted or received synchronously to a shift clock which is generated by the ST10F280. Half-duplex communication Baud (at 40MHz of f Figure 57 : Synchronous Mode of Serial Channel ASC0 CPU Clock S0R S0REN S0OEN Output S0LB TDx0/P3.10 Pin Input/Output Receive RxD0/P3 ...
Page 115
... ST10F280 f CPU = (S0BRS)] x [(S0BRL CPU (S0BRS Sync S0BRS = ‘1’ 40MHz CPU Reload Value Deviation Error (hexa) 0.0% / 0.0% 0000 / 0000 +2 ...
Page 116
... High Speed Synchronous Serial Channel (SSC) The High-Speed Synchronous Serial Interface SSC provides flexible communication between the ST10F280 and other microcontrollers, microprocessors or external peripherals. The SSC supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC itself (master ...
Page 117
... Table 26 : Synchronous Baud Rate and Reload Values Baud Rate Reserved use a reload value > 0. 10M Baud 5M Baud 2.5M Baud 1M Baud CPU 100K Baud 10K Baud 1K Baud ) 1 SSC 306 Baud ST10F280 Bit Time Reload Value --- --- 100ns 0001h 200ns 0003h 400ns 0007h 1 s 0013h 10 s 00C7h 100 s ...
Page 118
... Transceiver Transceiver CAN_H CAN bus CAN_H The ST10F280 also supports single CAN Bus multiple (dual) interfaces using the open drain option of the CANx_TxD output as shown in Fig- ure 60. Thanks to the OR-Wired Connection, only one transceiver is required. In this case the design of the application must take in account the wire length and the noise environment ...
Page 119
... Multiple CAN Bus The ST10F280 provides 2 CAN interfaces to support the kind of bus configuration shown in Figure 61. Figure 61 : Connection to Two Different CAN Buses (e.g. for gateway application) CAN1 RxD TxD RxD TxD CAN Transceiver Transceiver CAN_H CAN CAN_H bus 1 Figure 62 : CAN Module Address Map ...
Page 120
... ST10F280 Control / Status Register (EF00h/EE00h BOFF EWRN - RXOK TXOK Table 27 : CAN Control/Status Register Bit INIT Initialization 1: Software initialization of the CAN controller. While init is set, all message transfers are stopped. Setting init does not change the configuration registers and does not stop transmission or reception of a message in progress. The INIT bit is also set by hardware, following a busoff condition ...
Page 121
... CAN Interrupt Handling The on-chip CAN Module has one interrupt output, which is connected synchronization stage standard interrupt node in the ST10F280 in the same manner as all other interrupts of the peripherals. The control register for this interrupt is XP0IC (located at address F186h/C3h for CAN1 and F18Eh/C7h for CAN2 in the ESFR range) ...
Page 122
... ST10F280 Interrupt Register (EF02h/EE02h RESERVED Bit INTID Interrupt Identifier This number indicates the cause of the interrupt. When no interrupt is pending, the value will be “00”. Table 28 : INTID values and Corresponding Interrupt Sources INTID 00 Interrupt Idle: There is no interrupt request pending. 01 Status Change Interrupt: The CAN controller has updated (not necessarily changed) the status in the Control Register ...
Page 123
... Note The Mask of Last Message is ANDed with the Global Mask that corresponds to the incoming message. XReg Function XReg ST10F280 Reset Value: UUUUh BRP RW programmable acceptance Reset Value: UFUUh ID28...21 RW Reset Value: UUUUh ID28 ...
Page 124
... ST10F280 Lower Global Mask Long (EF0Ah/EE0Ah ID4...0 RW Bit ID28...0 Identifier (29 bit) Mask to filter incoming messages with extended identifier. Upper Mask of Last Message (EF0Ch/EE0Ch) XReg ID20...18 RW Lower Mask of Last Message (EF0Eh/EE0Eh) XReg ID4...0 RW Bit ID28...0 Identifier (29 bit) Mask to filter the last incoming message (Nr. 15) with standard or extended identifier (as configured). ...
Page 125
... NEWDAT has not been set. If there are several valid message objects with pending transmission request, the message with the lowest message number is transmitted first. XReg NEWDAT MSGVAL Function Reset Value: UUUUh TXIE RXIE ST10F280 1 0 INTPND RW 2 125/186 ...
Page 126
... ST10F280 15.6 - Arbitration Registers The arbitration Registers are used for acceptance filtering of incoming messages and to define the identifier of outgoing messages. Upper Arbitration Reg (EFn2h/EEn2h ID20...18 RW Lower Arbitration Reg (EFn4h/EEn4h ID4...0 RW Bit ID28...0 Identifier (29 bit) Identifier of a standard message (ID28...18 extended message (ID28...0). ...
Page 127
... Each of the different reset sources is indicated in the WDTCON register. The indicated bit are cleared with the EINIT instruction. The origine of the reset can be identi- fied during the initialization phase. SFR PONR LHWR SHWR R /2. CPU /128. CPU ST10F280 Reset Value: 00xxh SWR WDTR WDTIN 127/186 0 ...
Page 128
... ST10F280 The PONR flag of WDTCON register is set if the output voltage of the internal 3.3V supply falls below the threshold (typically 2V) of the power-on detection circuit. This circuit is efficient to detect major failures of the external 5V supply but if the internal 3.3V supply does not drop under 2 volts, the PONR flag is not set ...
Page 129
... This starting location will typically point to the general initialization routine. Timing of asynchronous reset sequence are summarized in Figure 65 TCL or 8 TCL Reset Configuration Latching point of PORT0 for system start-up configuration ST10F280 Conditions Power-on t > 1032 TCL RSTIN 4 TCL < t < 1032 TCL RSTIN WDT overflow ...
Page 130
... ST10F280 17.2 - Synchronous Reset (Warm Reset) A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high level. In order to properly activate the internal reset logic of the MCU, the RSTIN pin must be held low, at least, during 4 TCL (2 periods of CPU clock). The I/O pins are set to high impedance and RSTOUT pin is driven low ...
Page 131
... It is, for instance, the case of external memory running initialization routine before the execution of EINIT instruction. Bidirectional reset function is enabled by setting bit 3 (BDRSTEN) in SYSCON register. It only can be enabled during the initialization routine, before EINIT instruction is completed. ST10F280 1 and software resets, the EINIT ...
Page 132
... This pull-up charges the capacitor connected to RPD pin. If Bidirectional Reset function is not used, the simplest way to reset ST10F280 is to connect external components as shown in Figure 69. It works with reset from application (hardware or manual) and with power-on. The value of C1 ...
Page 133
... SRST instruction Trigger watchdog overflow Clr BDRSTEN Reset Sequence (512 CPU Clock Cycles) Asynchronous Reset From/to Exit Powerdown Circuit + C1 a) Manual Hardware Reset b) For Automatic Power-up Reset and interruptible power-down mode RPD + C0 RSTOUT Weak pull-down (~200 A) External Hardware ST10F280 RSTIN RPD 133/186 ...
Page 134
... ST10F280 Figure 70 : External Reset Hardware Circuitry RSTOUT RSTIN ST10F280 Table 33 : PORT0 Latched Configuration for the Different Resets X : Pin is sampled - : Pin is not sampled Sample event Software Reset - Watchdog Reset - Short Hardware Reset - Long Hardware Reset X X Power-On Reset X X Table 34 : PORT0 bit latched into the different registers after reset ...
Page 135
... POWER REDUCTION MODES Two different power reduction modes with differ- ent levels of power reduction have been imple- mented in the ST10F280, which may be entered under software control. In Idle mode the CPU is stopped, while the peripherals continue their operation. Idle mode can be terminated by any reset or interrupt request ...
Page 136
... ST10F280 18.2.1 - Protected Power Down Mode This mode is selected by clearing the bit PWD- CFG in register SYSCON to ‘0’. In this mode, the Power Down mode can only be entered if the NMI (Non Maskable Interrupt) pin is externally pulled low while the PWRDN instruction is executed. ...
Page 137
... Note: Due to internal pipeline, the instruction that V DD Stop pll D Q stop oscillator System clock Q cd follows the PWRDN intruction is executed before the CPU performs a call of the interrupt service routine when exiting power-down mode Pull-up RPD Weak Pull-down (~ 200 A) CPU and Peripherals clocks ST10F280 137/186 ...
Page 138
... ST10F280 Figure 73 : Powerdown Exit Sequence when Using an External Interrupt (PLL x 2) XTAL1 CPU clk internal Powerdown signal External Interrupt RPD ExitPwrd (internal) 138/186 delay for oscillator/pll stabilization ~ 2.5 V ...
Page 139
... SPECIAL FUNCTION REGISTER OVERVIEW The following table lists all SFRs which are implemented in the ST10F280 in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. ...
Page 140
... ST10F280 Table 35 : Special Function Registers Listed by Name (continued) Physical Name address CC6IC b FF84h CC7 FE8Eh CC7IC b FF86h CC8 FE90h CC8IC b FF88h CC9 FE92h CC9IC b FF8Ah CC10 FE94h CC10IC b FF8Ch CC11 FE96h CC11IC b FF8Eh CC12 FE98h CC12IC b FF90h CC13 FE9Ah CC13IC b FF92h ...
Page 141
... Port 2 Direction Control Register E3h Port 3 Direction Control Register E5h Port 4 Direction Control Register E7h Port 6 Direction Control Register E9h Port 7 Direction Control Register EBh Port 8 Direction Control Register Description ST10F280 Reset value - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h ...
Page 142
... ST10F280 Table 35 : Special Function Registers Listed by Name (continued) Physical Name address DPP0 FE00h DPP1 FE02h DPP2 FE04h DPP3 FE06h EXICON b F1C0h E EXISEL b F1DAh E IDCHIP F07Ch E IDMANUF F07Eh E IDMEM F07Ah E IDPROG F078h E IDX0 b FF08h IDX1 b FF0Ah MAH FE5Eh MAL FE5Ch MCW b FFDCh ...
Page 143
... PWM Module Up/Down Counter 3 18h PWM Module Pulse Width Register 0 19h PWM Module Pulse Width Register 1 1Ah PWM Module Pulse Width Register 2 1Bh PWM Module Pulse Width Register 3 Description ST10F280 Reset value - - 00h - - 00h 0000h - - 00h - - 00h - - 00h - - 00h 0000h ...
Page 144
... ST10F280 Table 35 : Special Function Registers Listed by Name (continued) Physical Name address PWMCON0 b FF30h PWMCON1 b FF32h PWMIC b F17Eh E QR0 F004h E QR1 F006h E QX0 F000h E QX1 F002h E RP0H b F108h E S0BG FEB4h S0CON b FFB0h S0EIC b FF70h S0RBUF FEB2h S0RIC b FF6Eh S0TBIC b F19Ch E S0TBUF FEB0h ...
Page 145
... C7h CAN2 Module Interrupt Control Register CBh XPWM Interrupt Control Register CFh PLL unlock Interrupt Control Register 12h XPER Configuration Register 8Eh Constant Value 0’s Register (read only) Description ST10F280 Reset value - - 00h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h ...
Page 146
... ST10F280 Table Registers Listed by Name Physical Name address CAN1BTR EF04h CAN1CSR EF00h CAN1GMS EF06h CAN1IR EF02h CAN1LAR1--15 EF14--EFF4h CAN1LGML EF0Ah CAN1LMLM EF0Eh CAN1MCR1--15 EF10--EFF0h CAN1MO1--15 EF1x--EFFxh CAN1UAR1--15 EF12--EFF2h CAN1UGML EF08h CAN1UMLM EF0Ch CAN2BTR EE04h CAN2CSR EE00h CAN2GMS ...
Page 147
... XPWM Pulse Width Register 3 XPWM Control Register 0 XPWM Control Register 1 Xtimer Control Register (Read / Write) Xtimer Current Value Register (Read / Write) Xtimer End Value Register (Read / Write) Xtimer Start Value Register (Read / Write) ST10F280 Reset value 0000h 0000h 0000h 0000h 0000h ...
Page 148
... Device Identifier 118h: ST10F280 identifier. 1 IDMEM (F07Ah / 3Dh MEMTYP R MEMSIZE Internal Memory Size is calculated using the following formula: Size = 4 x [MEMSIZE] (in K Byte) 080h for ST10F280 (512K Byte) MEMTYP Internal Memory Type 3h for ST10F280 (Flash memory). 1 IDPROG (F078h / 3Ch PROGVPP R PROGVDD ...
Page 149
... System Configuration Registers The ST10F280 has registers used for different configuration of the overall system. These registers are described below. SYSCON (FF12h / 89h STKSZ ROMS1 SGTDIS ROMEN BYTDIS CLKEN WRCFG CSCFG Notes: 1. These bit are set directly or indirectly according to PORT0 and EA pin configuration during reset sequence. ...
Page 150
... ST10F280 BYTDIS Disable/Enable Control for Pin BHE (Set according to data bus width) ‘0’: Pin BHE enabled ‘1’: Pin BHE disabled, pin may be used for general purpose I/O. ROMEN Internal Memory Enable (Set according to pin EA during reset) ‘0’: Internal Memory disabled: accesses to the Memory area use the external bus ‘ ...
Page 151
... The CS signal is generated for the duration of the read command CSWENx Write Chip Select Enable ‘0’: The CS signal is independent of the write command (WR,WRL,WRH) ‘1’: The CS signal is generated for the duration of the write command SFR BUSACT4 ALECTL4 Reset Value: 0000h BTYP MTTC4 RWDC4 ST10F280 MCTC RW 151/186 ...
Page 152
... ST10F280 RP0H (F108h / 84h WRC Write Configuration Control ‘0’: Pin WR acts as WRL, pin BHE acts as WRH ‘1’: Pins WR and BHE retain their normal function 2 CSSEL Chip Select Line Selection (Number of active CS outputs lines: CS2...CS0 lines: CS1...CS0 lines at all lines: CS4 ...
Page 153
... Port 2 pin P2.8 P2.9 P2.10...15 ESFR XP3IR XP3IE RW RW SFR Area xxIR xxIE RW RW Function Reset Value: 0000h EXI2SS EXI1SS RW RW Alternate Source CAN1_RxD CAN2_RxD Not used (zero) Reset Value 00h XP3ILVL RW Reset Value 00h ILVL RW ST10F280 1 0 EXI0SS GLVL GLVL RW 153/186 ...
Page 154
... ST10F280 XPERCON (F024h / 12h Bit CAN1EN CAN1 Enable Bit 0 Accesses to the on-chip CAN1 XPeripheral and its functions are disabled. P4.5 and P4.6 pins can be used as general purpose I/Os. Address range 00’EF00h-00’EFFFh is only directed to external memory if CAN2EN and XPWM bits are cleared also. ...
Page 155
... Absolute Maximum Ratings. 20.2 - Parameter Interpretation The parameters listed in the following tables represent the characteristics of the ST10F280 and its demands on the system. Where the ST10F280 logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics, is included in the “Symbol” column. ...
Page 156
... Power-down mode supply current PD Notes: 1. ST10F280 pins are equipped with low-noise output drivers which significantly improve the device’s EMI performance. These low-noise drivers deliver their maximum current only until the respective target output level is reached. After this, the output current is reduced. This results in increased impedance of the driver, which attenuates electrical noise from the connected PCB tracks. The current specified in column “ ...
Page 157
... This parameter value includes leakage currents. With all inputs (including pins configured as inputs 0. – 0. 0V, all outputs (including pins configured as outputs) disconnected REF Figure 74 : Supply / Idle Current as a Function of Operating Frequency 300 CCmax I CCtyp I IDmax I IDtyp 20 30 ST10F280 162mA 70mA 40 f [MHz] CPU 157/186 ...
Page 158
... ST10F280 20.3.1 - A/D Converter Characteristics ± 10 -40 to +125°C, 4. Table 38 : A/D Converter Characteristics Symbol V SR Analog Reference voltage AREF V SR Analog input voltage AIN I CC Reference supply current AREF running mode power-down mode C CC ADC input capacitance AIN Not sampling Sampling ...
Page 159
... A complete conversion will take 14 t time includes the conversion itself, the sample time and the time required to transfer the digital value to the result register. clock. This allows adjusting the A/D converter of the ST10F280 to the properties of the system: started, first the Fast programming the respective times to their absolute possible minimum ...
Page 160
... For timing purposes a port pin is no longer floating when V It begins to float when a 100mV change from the loaded V 20.4.2 - Definition of Internal Timing The internal operation of the ST10F280 is controlled by the internal CPU clock f edges of the CPU clock can trigger internal (for example pipeline) or external (for example bus cycles) operations ...
Page 161
... XTAL 20MHz XTAL 8MHz XTAL 1 to 40MHz XTAL 4MHz XTAL 2 to 80MHz f x 0.5 XTAL 16MHz XTAL and V IL ST10F280 TCL TCL TCL TCL TCL TCL 1 Notes Default configuration 2 4 Direct drive CPU clock via prescaler . IH2. 3 161/186 ...
Page 162
... PLL runs on its free-running frequency and delivers the clock signal for 162/186 20.4.6 - Oscillator Watchdog (OWD) An on-chip watchdog oscillator is implemented in the ST10F280. This feature is used for safety (i.e. the CPU operation with external crystal oscillator (using direct drive mode with or without prescaler). This ...
Page 163
... IH2 N 40. So for a period of 3 TCL periods = 4 - 3/ TCL 3.8/100) NOM = 3 TCL x 0.962 NOM = (36.075ns 40MHz) CPU 40 and 10MHz f 40MHz. CPU CPU XTAL / 2 XTAL 2 max min max – 100 x N – 2 – 10 – 2 – – – ST10F280 Unit 163/186 ...
Page 164
... ST10F280 Figure 79 : External Clock Drive XTAL1 20.4.9 - Memory Cycle Variables The tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. ...
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... TCL - 8 TCL - 8 -8 – – TCL + 6 2 TCL -9 TCL -9 – 2 TCL - – 3 TCL - – 3 TCL - – 4 TCL - – 2 TCL - 8 TCL - TCL - 8 TCL - TCL - – 3 TCL - TCL - 10 ST10F280 – ns – ns – ns – ns – – ns – – – ns – ns – ns – – ns 165/186 ...
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... ST10F280 Table 41 : Multiplexed Bus Characteristics Symbol Parameter t CC ALE fall. edge to RdCS, WrCS 42 (with RW delay ALE fall. edge to RdCS, WrCS 43 (no RW delay Address float after RdCS, 44 WrCS (with RW delay Address float after RdCS, 45 WrCS (no RW delay RdCS to Valid Data In 46 (with RW delay) ...
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... Figure 80 : External Memory Cycle : Multiplexed Bus, With / Without Read / Write Delay, Normal ALE CLKOUT t ALE t 6 CSx A23-A16 (A15-A8) BHE Read Cycle Address/Data Bus (P0) RD Write Cycle Address/Data Bus (P0) WR WRL WRH Address Address Address Data In Address Data Out ST10F280 167/186 ...
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... ST10F280 Figure 81 : External Memory Cycle: Multiplexed Mus, With / Without Read / Write Delay, Extended ALE CLKOUT t 5 ALE t 6 CSx t 6 A23-A16 (A15-A8) BHE Read Cycle t 6 Address/Data Bus (P0) RD Write Cycle Address/Data Bus (P0) WR WRL WRH 168/186 Address t 7 Address Address ...
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... Figure 82 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Normal ALE, Read / Write Chip Select CLKOUT t ALE t A23-A16 (A15-A8) BHE t Read Cycle Address/Data Bus (P0) RdCSx Write Cycle Address/Data Bus (P0) WrCSx Address Address Address Address Data Data Out ST10F280 169/186 ...
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... ST10F280 Figure 83 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Extended ALE, Read / Write Chip Select CLKOUT t 5 ALE t 6 A23-A16 (A15-A8) BHE Read Cycle t 6 Address/Data Bus (P0) RdCSx Write Cycle Address/Data Bus (P0) WrCSx 170/186 Address t 7 Address Address ...
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... TCL = 1 to 40MHz Minimum Maximum TCL - 8 – A TCL - 10 – TCL - 8 – A TCL - 8 – TCL - 9 – TCL - 9 – C – 2 TCL - – 3 TCL - – 3 TCL - – 4 TCL - – – 2 TCL - 8 – TCL - 8 TCL - – C TCL - 8 – – ( – > – – 3 TCL - ST10F280 171/186 ...
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... ST10F280 Table 42 : Demultiplexed Bus Characteristics Symbol Parameter t CC Latched CS hold after RD Address setup to RdCS, WrCS 82 (with RW-delay Address setup to RdCS, WrCS 83 (no RW-delay RdCS to Valid Data In 46 (with RW-delay RdCS to Valid Data In 47 (no RW-delay RdCS, WrCS Low Time 48 (with RW-delay RdCS, WrCS Low Time ...
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... Figure 84 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE CLKOUT t ALE CSx A23-A16 A15-A0 (P1) BHE Read Cycle Data Bus (P0) (D15-D8) D7-D0 RD Write Cycle Data Bus (P0) (D15-D8) D7-D0 WR WRL WRH Note: 1. Un-latched CSx = TCL =10 41u Address Data Out 41u 28h t 18 Data ST10F280 173/186 ...
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... ST10F280 Figure 85 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Extended ALE CLKOUT t ALE t CSx A23-A16 A15-A0 (P1) BHE Read Cycle Data Bus (P0) (D15-D8) D7-D0 RD Write Cycle Data Bus (P0) (D15-D8) D7-D0 WR WRL WRH 174/186 Address Data Data Out ...
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... Figure 86 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE, Read / Write Chip Select CLKOUT t ALE A23-A16 A15-A0 (P1) BHE Read Cycle Data Bus (P0) (D15-D8) D7-D0 RdCSx Write Cycle Data Bus (P0) (D15-D8) D7-D0 WrCSx Address Data Data Out ST10F280 175/186 ...
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... ST10F280 Figure 87 : External Memory Cycle: Demultiplexed Bus, no Read / Write Delay, Extended ALE, Read / Write Chip Select CLKOUT t ALE A23-A16 A15-A0 (P1) BHE Read Cycle Data Bus (P0) (D15-D8) D7-D0 RdCSx Write Cycle Data Bus (P0) (D15-D8) D7-D0 WrCSx 176/186 Address Data Data Out ...
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... refers to the current bus cycle. F Variable CPU Clock 1/2 TCL = 1 to 40MHz Minimum Maximum 2 TCL 2TCL TCL – 8.5 – TCL – 9.5 – – 4 – 12.5 – 2 – 2 TCL + 10 – 12.5 – 2 – 0 TCL - 12 ST10F280 177/186 ...
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... ST10F280 Figure 88 : CLKOUT and READY t 32 CLKOUT ALE RD, WR Synchronous READY t 58 Asynchronous READY 3) Notes: 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on RW-delay. 3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling point terminates the currently running bus cycle ...
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... HOLD HLDA BREQ CSx (P6.x) Others Notes: 1. The ST10F280 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pull-up) after t = -40 to +125° 50pF L Maximum CPU Clock ...
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... Notes: 1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be disactivated without the ST10F280 requesting the bus. 2. The next ST10F280 driven bus cycle may start here. ...
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... Unit Minimum Maximum 100 8 TCL 262144 TCL t – 300 – 300 10 – 10 – 15 – – -2 – 2 TCL + 12.5 – 4 TCL – 2 TCL – 305 Last Out Bit t t 307 308 Last.In Bit ST10F280 ns – ns – – ns – ns – ns – ns – ns 181/186 ...
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... ST10F280 20.4.14.2 Slave mode ±10 0V, CPU clock = 40MHz Symbol Parameter t SR SSC clock cycle time 310 t SR SSC clock high time 311 t SR SSC clock low time 312 t SR SSC clock rise time 313 t SR SSC clock fall time 314 CC Write data valid after shift edge ...
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... (208 + 25 BALLS) Inches (approx) Minimum Typical 0.077 0.019 0.024 0.054 0.022 0.024 0.030 0.902 0.906 0.800 0.902 0.906 0.800 0.50 0.049 0.053 ST10F280 Maximum 0.028 0.035 0.909 0.909 0.057 0.006 183/186 ...
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... A distinguishing feature is allowable on the bottom of the package to identify the terminal A1 corner. Exact shape and size of this feature is optional ORDERING INFORMATION Salestype ST10F280-JT3 184/186 Temperature range -40°C to +125°C Package PBGA 208 ( 1.96 mm) ...
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... ST10F280 185/186 ...
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... ST10F280 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...