C8051F334-GMR Silicon Laboratories Inc, C8051F334-GMR Datasheet - Page 94
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
C8051F334-GMR
Manufacturer Part Number
C8051F334-GMR
Description
IC 8051 MCU 2K FLASH 20MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Specifications of C8051F334-GMR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
For Use With
336-1451 - ADAPTER PROGRAM TOOLSTICK F330
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F334-GMR
Manufacturer:
ZILLTEK
Quantity:
3 340
Part Number:
C8051F334-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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10. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•
•
•
•
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled dur-
ing and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. Refer to
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source
Program execution begins at location 0x0000.
Px.x
Px.x
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
(Section “19.3. Watchdog Timer Mode” on page 201
System
Clock
Comparator 0
+
-
Section “13. Oscillators” on page 113
Detector
Missing
C0RSEF
Clock
(one-
shot)
Microcontroller
EN
CIP-51
Core
Figure 10.1. Reset Sources
WDT
PCA
EN
VDD
System Reset
Supply
Monitor
+
-
Rev. 1.7
Enable
(Software Reset)
SWRSF
for information on selecting and configuring
C8051F330/1/2/3/4/5
details the use of the Watchdog Timer).
'0'
Power On
Reset
Operation
FLASH
Errant
(wired-OR)
Reset
Funnel
/RST
97
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