MC908QY4ACDWE Freescale Semiconductor, MC908QY4ACDWE Datasheet - Page 25

• Manufacturer Part Number: MC908QY4ACDWE
• Description: IC MCU 8BIT 4K FLASH 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QY4ACDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Processor Series: HC08QY
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
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Addr.
↓
↓
ADC10 Data Register High
ADC10 Status and Control
Control Register (OSCSC)
ADC10 Data Register Low
TIM Channel 1 Status and
Control Register (TSC1)
Oscillator Trim Register
Register High (TCH1H)
ADC10 Clock Register
Register Low (TCH1L)
Register Name
Oscillator Status and
Register (ADSCR)
TIM Channel 1
TIM Channel 1
See page 135.
See page 137.
See page 137.
See page 100.
See page 101.
See page 46.
See page 48.
See page 48.
See page 48.
(OSCTRIM)
Reserved
Reserved
Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5)
(ADCLK)
(ADRH)
(ADRL)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
OSCOPT1 OSCOPT0
ADLPC
TRIM7
COCO
CH1F
Bit 15
Bit 7
Bit 7
AD7
R
R
0
0
0
1
0
0
0
0
0
= Unimplemented
CH1IE
TRIM6
ADIV1
Bit 14
AIEN
Bit 6
AD6
R
R
6
0
0
0
0
0
0
0
0
TRIM5
ADCO
ADIV0
ICFS1
Bit 13
Bit 5
AD5
R
R
5
0
0
0
0
0
0
0
1
0
Indeterminate after reset
Indeterminate after reset
ADICLK
ADCH4
TRIM4
MS1A
ICFS0
Bit 12
Bit 4
AD4
R
R
R
4
0
0
0
1
0
0
0
0
= Reserved
MODE1
ADCH3
ELS1B
ECFS1
TRIM3
Bit 11
Bit 3
AD3
R
R
3
0
0
0
1
0
0
0
0
MODE0
ADCH2
ECFS0
ELS1A
TRIM2
Bit 10
U = Unaffected
Bit 2
AD2
R
R
2
0
0
0
1
0
0
0
0
Direct Page Registers
ADLSMP
ECGON
ADCH1
TRIM1
TOV1
Bit 9
Bit 1
AD9
AD1
R
R
1
0
0
0
1
0
0
0
CH1MAX
ACLKEN
ECGST
ADCH0
TRIM0
Bit 0
Bit 8
Bit 0
AD8
AD0
R
R
0
0
0
1
0
0
0
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