MC908QY4ACDWE Freescale Semiconductor, MC908QY4ACDWE Datasheet - Page 49

• Manufacturer Part Number: MC908QY4ACDWE
• Description: IC MCU 8BIT 4K FLASH 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QY4ACDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Processor Series: HC08QY
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

ADIV[1:0] — ADC10 Clock Divider Bits
ADICLK — Input Clock Select Bit
MODE[1:0] — 10- or 8-Bit or Hardware Triggered Mode Selection
ADLSMP — Long Sample Time Configuration
ACLKEN — Asynchronous Clock Source Enable
Freescale Semiconductor
ADIV1 and ADIV0 select the divide ratio used by the ADC10 to generate the internal clock ADCK.
Table 3-3
If ACLKEN is clear, ADICLK selects either the bus clock or an alternate clock source as the input clock
source to generate the internal clock ADCK. If the alternate clock source is less than the minimum
clock speed, use the internally-generated bus clock as the clock source. As long as the internal clock
ADCK, which is equal to the selected input clock divided by ADIV, is at a frequency (f
the minimum and maximum clock speeds (considering ALPC), correct operation can be guaranteed.
These bits select 10- or 8-bit operation. The successive approximation converter generates a result
that is rounded to 8- or 10-bit value based on the mode selection. This rounding process sets the
transfer function to transition at the midpoint between the ideal code voltages, causing a quantization
error of ± 1/2
Reset returns 8-bit mode.
This bit configures the sample time of the ADC10 to either 3.5 or 23.5 ADCK clock cycles. This adjusts
the sample period to allow higher impedance inputs to be accurately sampled or to maximize
conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall
power consumption in continuous conversion mode if high conversion rates are not required.
This bit enables the asynchronous clock source as the input clock to generate the internal clock ADCK,
and allows operation in stop mode. The asynchronous clock source will operate between 1 MHz and
2 MHz if ADLPC is clear, and between 0.5 MHz and 1 MHz if ADLPC is set.
1 = The internal bus clock is selected as the input clock source
0 = The alternate clock source IS SELECTED
00 = 8-bit, right-justified, ADSCR software triggered mode enabled
01 = 10-bit, right-justified, ADSCR software triggered mode enabled
10 = Reserved
11 = 10-bit, right-justified, hardware triggered mode enabled
1 = Long sample time (23.5 cycles)
0 = Short sample time (3.5 cycles)
1 = The asynchronous clock is selected as the input clock source (the clock generator is only
0 = ADICLK specifies the input clock source and conversions will not continue in stop mode
enabled during the conversion)
shows the available clock configurations.
LSB
.
ADIV1
0
0
1
1
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
Table 3-3. ADC10 Clock Divide Ratio
ADIV0
0
1
0
1
Divide Ratio (ADIV)
1
2
4
8
Input clock ÷ 1
Input clock ÷ 2
Input clock ÷ 4
Input clock ÷ 8
Clock Rate
ADCK
) between
Registers
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