MC56F8014VFAE Freescale Semiconductor, MC56F8014VFAE Datasheet
MC56F8014VFAE
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Data Sheet Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8014 Rev. 11 05/2008 freescale.com ...
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... STOP mode from 8MHz to 4MHz. 10-12, changed the typical relaxation oscillator output frequency in Standby mode 56F8014 Technical Data, Rev. 11 Section 6.3.1.7, clarified Table Table 2-3; 10-4; moved input current high/low 10-5; reorganized Table 10-19; clarified title of Freescale Semiconductor 10-4, ...
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... Revised • Added MC56F8014MFAE to • Fixed miscellaneous errors. Rev.11 • Updated temperature information in Please see http://www.freescale.com for the most current data sheet revision. Freescale Semiconductor Description of Change through a 2.2K resistor. DD value from 4.7 μF to 2.2 μF. 2-3, changed V CAP 2-3, changed the input type for FAULT3 (was “ ...
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... Digital Reg Analog Reg Low-Voltage 16-Bit Supervisor 56800E Core Data ALU Bit -> 36-Bit MAC Manipulation Three 16-bit Input Registers Unit Four 36-bit Accumulators R/W Control System Bus Control P System O O Clock Integration S R Module Generator* C *Includes On-Chip Relaxation Oscillator Freescale Semiconductor ...
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... Register Descriptions . . . . . . . . . . . . . . . . . 64 6.4. Clock Generation Overview . . . . . . . . . . . . 77 6.5. Power-Down Modes . . . . . . . . . . . . . . . . . . 77 6.6. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.7. Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.8. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Freescale Semiconductor Part 7: Security Features . . . . . . . . . . . . . . .82 7.1. Operation with Security Enabled . . . . . . . . . 82 7.2. Flash Access Lock and Unlock Mechanisms 83 7.3. Product Analysis Part 8: General Purpose Input/Output (GPIO) ...
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... Center-aligned and Edge-aligned PWM signal mode — Three programmable fault inputs with programmable digital filter — Double-buffered PWM registers 6 that prevent unauthorized users from gaining access to the internal Flash using Flash 56F8014 Technical Data, Rev. 11 Freescale Semiconductor ...
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... General-Purpose I/O (GPIO) pins with 5V tolerance • Integrated Power-On Reset and Low-Voltage Interrupt Module • Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals • Clock Sources: — On-chip relaxation oscillator Freescale Semiconductor 2 C) port 56F8014 Technical Data, Rev. 11 56F8014 Features 7 ...
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... The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs 8 56F8014 Technical Data, Rev Quad Timer—support various Freescale Semiconductor ...
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... Timer3 output can be used to drive PWM 4 and 5 • ADC conversion result: — Signal of over/under limit of ADC sample 0 can be used to drive PWM 0 and 1 — Signal of over/under limit of ADC sample 1 can be used to drive PWM 2 Freescale Semiconductor Figure 1-1, Figure 1-2, and Figure 1-3 details how the device’ ...
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... Unit Decoder (AGU) Interrupt M01 Unit N3 Looping Unit Data Y0 Arithmetic X0 Logic Unit (ALU) MAC and ALU Multi-Bit Shifter 56F8014 Technical Data, Rev. 11 ALU1 ALU2 Program R3 Memory XAB1 XAB2 PAB Data / Program PDB RAM CDBW CDBR XDB2 A0 B0 IPBUS C0 Interface D0 Freescale Semiconductor ...
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... CLKIN) 8 GPIOAn GPIO A 8 GPIOBn GPIO B 6 GPIOCn GPIO C 4 GPIODn GPIO D Freescale Semiconductor To/From IPBus Bridge IPBus (Continues on Figure 1-3) Figure 1-2 Peripheral Subsystem 56F8014 Technical Data, Rev. 11 Multiple Frequency PWM Output Interrupt Controller Low-Voltage Interrupt POR & LVI System POR ...
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... MISO, MOSI 2 to PWM 3 ANA0 ANA2 REFH REFL ANB2 V 2 ANB0 56F8014 Technical Data, Rev. 11 PWM0 - 3 GPIOA0 - 3 PWM4, 5 Fault1, 2 T2, 3 GPIOA4 - 5 Fault0 GPIOA6 Fault3 T1 GPIOB5 T0 CLKO GPIOB4 GPIOB6 - 7 GPIOB0 - 1 T2, 3 GPIOB2 - 3 ANA0 ANA2 GPIOC0 ANB2 , V REFH REFL GPIOC2, 6 ANB0 GPIOC4 Freescale Semiconductor ...
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... Product Documentation The documents listed in Table 1-1 56F8014. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at: http://www.freescale.com Table 1-1 56F8014 Chip Documentation Topic DSP56800E Detailed description of the 56800E family architecture, Reference Manual ...
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... Pins in this section can function as TMR Pins can function as PWM and GPIO. 4. Pins in this section can function Table 2-2, each table row describes the signal or Functional Group ) DDA ) SSA and GPIO and GPIO. 56F8014 Technical Data, Rev. 11 Number of Pins Freescale Semiconductor ...
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... GPIOB4 GPIOB4, T0, CLKO 20 GPIOA5 GPIOA5, PWM5, FAULT2 GPIOB0 GPIOB0, SCLK, SCL 22 GPIOA4 GPIOA4, PWM4, FAULT1 GPIOA2 GPIOA2, PWM2 24 VCAP V CAP Freescale Semiconductor Table 2-2 56F8014 Pins Peripherals: GPIO I2C SCI SPI ADC B1 SDA SS B7 SCL TXD B5 C4 ANB0 C5 ANB1 C6 ANB2, V REFL ...
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... TDO, GPIOD1 32 GPIOB6 GPIOB6, RXD, SDA, CLKIN 16 Table 2-2 56F8014 Pins (Continued) Peripherals: GPIO I2C SCI SPI ADC SDA RXD 56F8014 Technical Data, Rev. 11 Quad Power & PWM JTAG Timer Ground V DD_IO V SS_IO PWM1 PWM0 TDI TMS TDO Freescale Semiconductor Misc. CLKIN ...
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... RESET RESET (GPIOA7) GPIOB4 (T0, CLKO) Timer Port or GPIO GPIOB5 (T1, FAULT3) TCK (GPIOD2) TMS (GPIOD3) JTAG/ EOnCE Port TDI (GPIOD0) or GPIO TDO (GPIOD1) Figure 2-1 56F8014 Signals Identified by Functional Group (32-Pin LQFP) Freescale Semiconductor V DD_IO 1 V SS_IO 2 V DDA 1 V SSA 1 56F8014 ...
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... Clock Input — This pin serves as an optional external clock input. After reset, the default state is GPIOB6. The alternative peripheral functionality is controlled via the SIM (See CLKMODE bit of the OCCS Oscillator Control Register. 56F8014 Technical Data, Rev. 11 Signal Description Section 10.2. serial data line. Section 6.3.8) and the Freescale Semiconductor ...
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... Input/ Output (T0) Input/ Output (CLKO) Output Return to Table 2-2 Freescale Semiconductor State During Reset Input with Port B GPIO — This GPIO pin can be individually programmed as internal an input or output pin. pull-up enabled Transmit Data — SCI transmit data output or transmit / receive in single wire opeation. ...
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... Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TDI. 56F8014 Technical Data, Rev. 11 Signal Description Section 6.3.8. through a 2.2K resistor if this pin DD Freescale Semiconductor ...
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... Output 4. This signal is also brought out on the GPIOB6 pin. Return to Table 2-2 Freescale Semiconductor State During Reset Output Test Data Output — This tri-stateable output pin provides a serial output data stream from the JTAG/EOnCE port driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK. Port D GPIO — ...
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... Port A GPIO — This GPIO pin can be individually programmed as internal an input or output pin. pull-up enabled PWM0 — This is one of the six PWM output pins. After reset, the default state is GPIOA0. 56F8014 Technical Data, Rev. 11 Signal Description Section 6.3.8. Section 6.3.8. Freescale Semiconductor ...
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... Input 8 Input/ (T3 ) Output 8. This signal is also brought out on the GPIOB3 pin. Return to Table 2-2 Freescale Semiconductor State During Reset Input with Port A GPIO — This GPIO pin can be individually programmed as internal an input or output pin. pull-up enabled PWM1 — This is one of the six PWM output pins. ...
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... After reset, the default state is ANA3. Analog ANB0 — Analog input to ADC B, channel 0 Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is ANB0. 56F8014 Technical Data, Rev. 11 Signal Description Freescale Semiconductor ...
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... Output ANB3 7 Input (GPIOC7) Input/ Output Return to Table 2-2 Freescale Semiconductor State During Reset Analog ANB1 — Analog input to ADC B, channel 1 Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is ANB1. ...
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... The 2X system clock source output from the OCCS can be described by one of the following equations: 2X system frequency = oscillator frequency 2X system frequency = (oscillator frequency (postscaler) where: postscaler = 16 PLL output divider The SIM is responsible for further dividing these frequencies by two, which will insure a 50% duty cycle in the system clock output. 26 56F8014 Technical Data, Rev. 11 Freescale Semiconductor ...
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... For more information on these registers, please refer to the 56F801X Peripheral Reference Manual. 3.3.1 External Clock Source The recommended method of connecting an external clock is illustrated in source is connected to GPIOB6 / RXD / SDA / CLKIN. Figure 3-1 Connecting an External Clock Signal using GPIOB6 / RXD / SDA / CLKIN Freescale Semiconductor 56F8014 GPIOB6/RXD/SDA/CLKIN External Clock 56F8014 Technical Data, Rev. 11 Operating Modes Figure 3-1 ...
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... Bus Interface and Control PRECS MSTR_OSC Postscaler ÷ 3 (÷ 16, 32) ÷ 2 Postscaler (÷ 16, 32) LCK Loss of Loss of Reference Clock Interrupt Reference Clock Detector 56F8014 Technical Data, Rev. 11 Bus Interface SYS_CLK_x2 source to the SIM (64MHz max) ZSRC PLLCOD HS PERF CLK (96MHz max) Freescale Semiconductor ...
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... By default, the chip reset address and COP reset address will correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions. Freescale Semiconductor Table 4-1. Flash memories’ restrictions are Table 4-1 ...
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... P:$36 SPI Transmitter Empty P:$38 SCI Transmitter Empty P:$3A SCI Transmitter Idle P:$3C SCI Reserved P:$3E SCI Receiver Error P:$40 SCI Receiver Full Reserved P:$ P:$48 Timer Channel 0 P:$4A Timer Channel 1 (Continues next page) 56F8014 Technical Data, Rev Interrupt Function 2 Freescale Semiconductor ...
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... P: $00 7FFF P: $00 2000 P: $00 1FFF P: $00 0000 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Data space starting at address X: $00 0000; see Figure Freescale Semiconductor Vector Base Address + P:$4C Timer Channel 2 P:$4E Timer Channel 3 P:$50 ADCA Conversion Complete ...
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... Table 4-4 Data Memory Map Memory Allocation EOnCE 256 locations allocated RESERVED On-Chip Peripherals 4096 locations allocated RESERVED Reserved RESERVED 2 On-Chip Data RAM 4KB Dual Port RAM Figure 4-1 Dual Port RAM 56F8014 Technical Data, Rev Data EOnCE Reserved Peripherals Reserved RAM Freescale Semiconductor ...
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... Table 4-6 summarizes base addresses for the set of peripherals on the 56F8014 device. Peripherals are listed in order of the base address. Freescale Semiconductor Table 4-5 EOnCE Memory Map Transmit Register Upper Word Receive Register Upper Word ...
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... Comparator Load Register 1 $9 Comparator Load Register 2 $A Comparator Status and Control Register Reserved $10 Compare Register 1 $11 Compare Register 2 56F8014 Technical Data, Rev. 11 Table Number 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 Freescale Semiconductor ...
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... TMR2_CNTR TMR2_CTRL TMR2_SCTRL TMR2_CMPLD1 TMR2_CMPLD2 TMR2_CSCTRL TMR3_COMP1 TMR3_COMP2 TMR3_CAPT TMR3_LOAD TMR3_HOLD TMR3_CNTR TMR3_CTRL TMR3_SCTRL TMR3_CMPLD1 TMR3_CMPLD2 TMR3_CSCTRL Freescale Semiconductor (TMR_BASE = $00 F000) Address Offset Register Description $12 Capture Register $13 Load Register $14 Hold Register $15 Counter Register $16 Control Register $17 Status and Control Register $18 Comparator Load Register 1 ...
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... Interrupt Priority Register 1 $2 Interrupt Priority Register 2 $3 Interrupt Priority Register 3 $4 Interrupt Priority Register 4 $5 Vector Base Address Register $6 Fast Interrupt Match 0 Register $7 Fast Interrupt Vector Address Low 0 Register $8 Fast Interrupt Vector Address High 0 Register 56F8014 Technical Data, Rev. 11 Freescale Semiconductor ...
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... ADC_RSLT1 ADC_RSLT2 ADC_RSLT3 ADC_RSLT4 ADC_RSLT5 ADC_RSLT6 ADC_RSLT7 ADC_LOLIM0 ADC_LOLIM1 ADC_LOLIM2 ADC_LOLIM3 ADC_LOLIM4 ADC_LOLIM5 Freescale Semiconductor (ITCN_BASE = $00 F060) Address Offset Register Description $9 Fast Interrupt Match 1 Register $A Fast Interrupt Vector Address Low 1 Register $B Fast Interrupt Vector Address High 1 Register $C IRQ Pending Register 0 $D IRQ Pending Register 1 ...
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... Offset Register 5 $27 Offset Register 6 $28 Offset Register 7 $29 Power Control Register $2A Voltage Reference Register Reserved (SCI_BASE = $00 F0B0) Address Offset Register Description $0 Baud Rate Register $1 Control Register 1 $2 Control Register 2 $3 Status Register $4 Data Register 56F8014 Technical Data, Rev. 11 Freescale Semiconductor ...
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... Register Acronym COP_CTRL COP_TOUT COP_CNTR Table 4-15 Clock Generation Module Registers Address Map Register Acronym OCCS_CTRL OCCS_DIVBY OCCS_STAT OCCS_SHUTDN OCCS_OCTRL Freescale Semiconductor (SPI_BASE = $00 F0C0) Address Offset Register Description $0 Status and Control Register $1 Data Size and Control Register $2 Data Receive Register $3 Data Transmit Register ...
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... Data Register $2 Data Direction Register $3 Peripheral Enable Register $4 Interrupt Assert Register $5 Interrupt Enable Register $6 Interrupt Edge Polarity Register $7 Interrupt Pending Register $8 Interrupt Edge-Sensitive Register $9 Push-Pull Output Mode Control Register $A Raw Data Register $B Drive Strength Control Register 56F8014 Technical Data, Rev. 11 Freescale Semiconductor ...
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... Table 4-19 GPIOD Registers Address Map Register Acronym GPIOD_PUPEN GPIOD_DATA GPIOD_DDIR GPIOD_PEREN GPIOD_IASSRT GPIOD_IEN GPIOD_IEPOL GPIOD_IPEND GPIOD_IEDGE GPIOD_PPOUTM GPIOD_RDATA GPIOD_DRIVE Freescale Semiconductor (GPIOC_BASE = $00 F120) Address Offset Register Description $0 Pull-up Enable Register $1 Data Register $2 Data Direction Register $3 Peripheral Enable Register $4 Interrupt Assert Register ...
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... F160) Address Offset $0 Control Register $1 Status Register (FM_BASE = $00 F400) Address Offset Register Description $0 Clock Divider Register $1 Configuration Register $2 Reserved $3 Security High Half Register $4 Security Low Half Register $ Reserved $10 Protection Register $11 - $12 Reserved 56F8014 Technical Data, Rev. 11 Register Description Freescale Semiconductor ...
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... During wait and stop modes, the system clocks and the 56800E core are turned off. The ITCN can wake the core and restart system clocks by signaling a pending IRQ to the System Integration Module (SIM) to Freescale Semiconductor (FM_BASE = $00 F400) Address Offset ...
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... The core then fetches the instruction from the indicated vector adddress and not a JSR, the core starts its Fast Interrupt handling. 44 SR[8] Exceptions Permitted 0 Priorities Priorities Priorities Priority 3 56F8014 Technical Data, Rev. 11 Exceptions Masked None Priority 0 Priorities 0, 1 Priorities Fast Interrupt Freescale Semiconductor ...
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... A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN module has 16 registers. Register Base Address + Acronym IPR0 $0 IPR1 $1 IPR2 $2 Freescale Semiconductor any0 Level 0 46 -> Priority Encoder any3 Level 3 46 -> ...
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... Fast Interrupt 1 Vector Address High Register IRQ Pending Register 0 IRQ Pending Register 1 IRQ Pending Register 2 Reserved Interrupt Control Register Reserved 56F8014 Technical Data, Rev. 11 Section Location 5.5.4 5.5.5 5.5.6 5.5.7 5.5.8 5.5.9 5.5.10 5.5.11 5.5.12 5.5.13 5.5.14 5.5.15 5.5.16 Freescale Semiconductor ...
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... ICTRL W Reserved = Reserved Figure 5-2 ITCN Register Map Summary 5.5.1 Interrupt Priority Register 0 (IPR0) Base + $ Read 0 LVI IPL Write RESET Figure 5-3 Interrupt Priority Register 0 (IPR0) Freescale Semiconductor RX_REG IPL TX_REG IPL 0 0 GPIOC IPL GPIOD IPL FM_CBE IPL 0 0 SCI_RERR ...
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... IPL)— Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through disabled by default. • IRQ disabled (default) • IRQ is priority level 1 • IRQ is priority level 2 • IRQ is priority level 3 48 56F8014 Technical Data, Rev. 11 Freescale Semiconductor ...
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... GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor GPIOD IPL FM_CBE IPL ...
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... FM Error Interrupt Priority Level (FM_ERR IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 50 56F8014 Technical Data, Rev. 11 Freescale Semiconductor ...
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... IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.5.3.3 Reserved—Bits 11–10 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. Freescale Semiconductor SCI_TIDL IPL SCI_XMIT IPL SPI_XMIT IPL SPI_RCV IPL ...
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... Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 52 56F8014 Technical Data, Rev. 11 Freescale Semiconductor ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor TMR_2 IPL TMR_1 IPL TMR_0 IPL ...
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... Interrupt Priority Register 4 (IPR4) Base + $ Read Write RESET Figure 5-7 Interrupt Priority Register 4 (IPR4) 5.5.5.1 Reserved—Bits 15–8 This bit field is reserved or not implemented read as 0 and cannot be modified by writing PWM_F IPL 56F8014 Technical Data, Rev ADC_ZC_LE ADCB_CC PWM_RL IPL IPL IPL Freescale Semiconductor ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor 56F8014 Technical Data, Rev. 11 Register Descriptions 55 ...
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... Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest-priority level 2 interrupt regardless of its location in the interrupt table prior to being declared as Fast Interrupt. Fast Interrupt 0 has priority over fast Interrupt 1. To determine the vector number of each IRQ, refer to the vector table VECTOR_BASE_ADDRESS 56F8014 Technical Data, Rev FAST INTERRUPT Freescale Semiconductor ...
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... These values determine which IRQ will be Fast Interrupt 1. Fast Interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having jump table first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast Freescale Semiconductor 12 11 ...
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... Figure 5-15 IRQ Pending Register 0 (IRQP0) 5.5.13.1 IRQ Pending (PENDING)—Bits 15–1 This register combines with IRQP1 and IRQP2 to represent the pending IRQs for interrupt vector numbers 2 through 45 FAST INTERRUPT 1 VECTOR ADDRESS LOW PENDING[16: 56F8014 Technical Data, Rev FAST INTERRUPT 1 VECTOR ADDRESS HIGH Freescale Semiconductor ...
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... This register combines with IRQP0 and IRQP1 to represent the pending IRQs for interrupt vector numbers 2 through 45. • IRQ pending for this vector number • IRQ pending for this vector number 5.5.16 Interrupt Control Register (ICTRL) $Base + $ Read INT IPIC Write RESET Figure 5-18 Interrupt Control Register (ICTRL) Freescale Semiconductor PENDING[32:17 PENDING[45:33] ...
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... Interrupt Disable (INT_DIS)—Bit 5 This bit allows all interrupts to be disabled. • Normal operation (default) • All interrupts disabled 60 Current Interrupt Required Nested Priority Level Exception Priority No interrupt or SWILP Priorities Priority 0 Priorities Priority 1 Priorities 2, 3 Priority Priority 3 56F8014 Technical Data, Rev. 11 Freescale Semiconductor ...
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... Illegal Instruction • SW Interrupt 3 • HW Stack Overflow • Misaligned Long Word Access • SW Interrupt 2 • SW Interrupt 1 Freescale Semiconductor Table 5-4 Reset Summary Priority Source RST Figure 5-19 . RESET_VECTOR_ADR Figure 5-19 Reset Interface 56F8014 Technical Data, Rev. 11 Characteristics Core reset from the SIM ...
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... Stop mode shuts down the 56800E core, system clock, and peripheral clock — Wait mode shuts down the 56800E core and unnecessary system clock operation — Run mode supports full part operation • Controls, with write protection, the enable/disable of 56800E core WAIT and STOP instructions 62 56F8014 Technical Data, Rev. 11 Freescale Semiconductor ...
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... Timer channel Stop mode clocking controls • SCI Stop mode clocking control to support LIN Sleep mode stop recovery • Short addressing location control • Registers for containing the JTAG ID of the chip • Controls output to CLKO pin Freescale Semiconductor 56F8014 Technical Data, Rev. 11 Features 63 ...
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... GPIO Peripheral Select Register Peripheral Clock Enable Register I/O Short Address Location High Register I/O Short Address Location Low Register 56F8014 Technical Data, Rev. 11 Section Location 6.3.1 6.3.2 6.3.3 6.3.3 6.3.3 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.3.10 6.3.10 Freescale Semiconductor ...
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... TC1_ Write RESET Figure 6-2 SIM Control Register (SIM_CTRL) 6.3.1.1 Timer Channel 3 Stop Disable (TC3_SD)—Bit 15 This bit enables the operation of the Timer Channel 3 peripheral clock in Stop mode. • Timer Channel 3 disabled in Stop mode Freescale Semiconductor TC1_ TC0_ SCI_ TC3_ SD SD ...
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... OnCE Enable (ONCEEBL)—Bit 5 • OnCE clock to 56800E core enabled when core TAP is enabled • OnCE clock to 56800E core is always enabled 6.3.1.10 Software Reset (SWRST)—Bit 4 Writing 1 to this field will cause the part to reset. 66 56F8014 Technical Data, Rev. 11 Freescale Semiconductor ...
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... When set, this bit indicates that the previous system reset occurred as a result of a software reset (written RST bit in the SIM_CTRL register). It will not be set if a COP, external, or POR reset also occurred. 6.3.2.3 COP Reset (COPR)—Bit 4 When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly Freescale Semiconductor ...
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... Most Significant Half of JTAG ID (SIM_MSHID) This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $01F2. Base + $ Read Write RESET Figure 6-5 Most Significant Half of JTAG ID (SIM_MSHID Software Control Data 56F8014 Technical Data, Rev Freescale Semiconductor ...
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... CLKO Select Register (SIM_CLKOUT) The CLKO select register can be used to multiplex out selected clocks generated inside the clock generation and SIM modules. All functionality is for test purposes only and is subject to unspecified latencies. Glitches may be produced when the clock is enabled or switched. Freescale Semiconductor ...
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... Reserved for factory test—Continuous system clock • 01001 = Reserved for factory test—OCCS MSTR OSC clock • 01011 = Reserved for factory test—ADC clock • 01100 = Reserved for factory test—JTAG TCLK PWM PWM PWM1 PWM0 56F8014 Technical Data, Rev CLK CLKOSEL DIS Freescale Semiconductor ...
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... This bit selects the clock speed for the Quad Timer module. • Quad Timer module clock rate equals system clock rate maximum 32 MHz (default) • Quad Timer module clock rate equals three times sytem clock rate maximum 96 MHz Freescale Semiconductor GPIOB_PEREN Register GPIO Controlled 0 1 ...
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... Note: The PRECS bit in the OCCS Oscillator Control register can enable this pin as the 72 module’s clock is disabled. See PWM when Using PWM Reload Pulse Quad Timer Clock Speed 56F8014 Technical Data, Rev. 11 Section Section 6.3.1.7), Table 6-2. Section 6.3.9. Section 6.3.1.7), Table 6- Freescale Semiconductor ...
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... SCL — I2C Serial Clock 6.3.8.12 Configure GPIOA5[1:0] (CFG_A5)—Bits 3–2 These bits select the alternate function for GPIOA5. • PWM5 — PWM5 output (default) • PWM5 — PWM5 output • FAULT2 — PWM FAULT2 input Freescale Semiconductor 56F8014 Technical Data, Rev. 11 Register Descriptions 73 ...
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... This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.3.9.5 Timer Clock Enable (TMR)—Bit 6 • The clock is not provided to the Quad Timer module (the Quad Timer module is disabled module (the I C module is disabled) 56F8014 Technical Data, Rev TMR SCI SPI Freescale Semiconductor 0 PWM 0 ...
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... The I/O short address mode allows the instruction to specify the lower six bits of address; the upper address bits are not directly controllable. This register set allows limited control of the full address, as shown in Figure 6-12. Freescale Semiconductor 56F8014 Technical Data, Rev. 11 Register Descriptions 75 ...
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... Input/Output Short Address Location (ISAL[23:22])—Bit 1–0 This field represents the upper two address bits of the “hard coded” I/O short address. 76 “ Hard Coded” Address Portion 6 Bits from I/O Short Address Mode Instruction 56F8014 Technical Data, Rev. 11 Instruction Portion ISAL[23:22 Freescale Semiconductor 0 1 ...
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... Timer channels and PWM but require the PLL and selected. Refer to the 56F801X Peripheral Reference Manual for further details. 6.5 Power-Down Modes The 56F8014 operates in one of five Power-Down modes, as shown in Table 6-3 Clock Operation in Power-Down Modes Mode Core Clocks Run Core and memory clocks disabled Freescale Semiconductor ISAL[21: ...
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... The user configures the OCCS and SIM to enter Standby mode as shown in the previous description, followed by powering down the oscillator (ROPD). The only possible recoveries from this mode are: 1. External reset 2. Power-on reset 56F8014 Technical Data, Rev. 11 Description Table 6-3. Run, Wait, and Stop Freescale Semiconductor ...
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... Relaxation Oscillator Clock as their time base since other system clocks are inactive during this phase of reset. 1. The Quad Timer and PWM modules can be operated at three times the IPBus clock frequency. Freescale Semiconductor Figure 6-15. The two asynchronous sources are the ...
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... Resets may be asserted asynchronously, but they are always released internally on a rising edge of the system clock. 80 EXTENDED_POR CLKGEN_RST Delay 32 MSTR_OSC Clocks pulse shaper Delay 32 sys clocks pulse shaper 56F8014 Technical Data, Rev. 11 JTAG Memory Subsystem OCCS PERIP_RST Peripherals 56800E Delay 32 sys clocks pulse shaper CORE_RST Freescale Semiconductor ...
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... SYS_CLK cycles to create CORE_RST. Both PERIP_RST and CORE_RST should be released on the negative edge of SYS_CLK_D as shown. This phased releasing of system resets is necessary to give some peripherals (for example, the Flash interface unit) set-up time prior to the 56800E core becoming active. Freescale Semiconductor 56F8014 Technical Data, Rev. 11 Clocks ...
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... Refer to the flash 82 for combined reset extension Switch on falling OSC_CLK 96 MSTR_OSC cycles 32 SYS_CLK cycles delay Switch on falling SYS_CLK 56F8014 Technical Data, Rev. 11 Switch on falling SYS_CLK 32 SYS_CLK cycles delay Freescale Semiconductor ...
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... Flash Lockout Recovery Without Mass Erase The user can un-secure a secured device by programming the word $0000 into program memory location $00 1FF7. After completing the programming, both the JTAG TAP controller and the device must be reset Freescale Semiconductor sequence via JTAG, 56F8014 Technical Data, Rev ...
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... GPIO Port Pins in 56F8014 8-1. The specific mapping of GPIO port pins is shown in Table 8-1 GPIO Ports Configuration Peripheral Function PWM, Reset SPI, SCI, Timer ADC JTAG 56F8014 Technical Data, Rev. 11 Table 8-2. Reset Function GPIO, except GPIOA7 GPIO Analog JTAG Freescale Semiconductor ...
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... FAULT0 GPIOA7 RESET GPIOB0 SCLK / SCL GPIOB1 SS / SDA GPIOB2 MISO / T2 GPIOB3 MOSI / T3 GPIOB4 T0 / CLKO GPIOB5 T1 / FAULT3 Freescale Semiconductor LQFP Package Pin 28 Defaults Defaults toA1 23 Defaults to A2 Not bonded out in 56F8014 Defaults SIM register SIM_GPS is used to select between PWM4, FAULT1, and T2 Defaults to A4 ...
Page 86
... SIM register SIM_GPS is used to select between TXD and SCL Defaults to B7 Defaults to ANA0 Defaults to ANA1 Defaults to ANA2 Defaults to ANA3 Defaults to ANB0 Defaults to ANB1 Defaults to ANB2 Defaults to ANB3 Defaults to TDI Defaults to TDO Defaults to TCK Defaults to TMS 8-1 through 8-4 summarize register Freescale Semiconductor ...
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... Add. Register Acronym 15 Offset GPIOA_PUPEN GPIOA_DATA GPIOA_DDIR GPIOA_PEREN GPIOA_IASSRT GPIOA_IEN GPIOA_IEPOL GPIOA_IPEND GPIOA_IEDGE GPIOA_PPOUTM GPIOA_RDATA GPIOA_DRIVE Figure 8-1 GPIOA Register Map Summary Freescale Semiconductor Read as 0 Reserved Reset 56F8014 Technical Data, Rev. 11 Reset Values IEN IEPOL IPR IES OEN RAW DATA ...
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... Add. Register Acronym 15 Offset GPIOB_PUPEN GPIOB_DATA GPIOB_DDIR GPIOB_PEREN GPIOB_IASSRT GPIOB_IEN GPIOB_IEPOL GPIOB_IPEND GPIOB_IEDGE GPIOB_PPOUTM GPIOB_RDATA GPIOB_DRIVE Figure 8-2 GPIOB Register Map Summary Read as 0 Reserved Reset 56F8014 Technical Data, Rev IEN IEPOL IPR IES OEN RAW DATA DRIVE Freescale Semiconductor ...
Page 89
... Add. Register Acronym 15 Offset GPIOC_PUPEN GPIOC_DATA GPIOC_DDIR GPIOC_PEREN GPIOC_IASSRT GPIOC_IEN GPIOC_IEPOL GPIOC_IPEND GPIOC_IEDGE GPIOC_PPOUTM GPIOC_RDATA GPIOC_DRIVE Figure 8-3 GPIOC Register Map Summary Freescale Semiconductor Read as 0 Reserved Reset 56F8014 Technical Data, Rev. 11 Reset Values IEN IEPOL IPR IES OEN RAW DATA ...
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... Add. Register Acronym 15 Offset GPIOD_PUPEN GPIOD_DATA GPIOD_DDIR GPIOD_PEREN GPIOD_IASSRT GPIOD_IEN GPIOD_IEPOL GPIOD_IPEND GPIOD_IEDGE GPIOD_PPOUTM GPIOD_RDATA GPIOD_DRIVE Read as 0 Reserved 56F8014 Technical Data, Rev IEN IEPOL IPR IES OEN RAW DATA DRIVE Freescale Semiconductor ...
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... Unless otherwise stated, all specifications within this chapter apply over the temperature range of -40ºC to 125ºC ambient temperature over the following supply ranges 0V DDA Freescale Semiconductor Reset are stress ratings only, and functional operation at the maximum = 3.0–3.6V, CL < 50pF 32MHz OP 56F8014 Technical Data, Rev. 11 56F8014 Information in the package. DD ...
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... Technical Data, Rev. 11 higher than Min Max Unit -0.3 4.0 - 0.3 4.0 - 0.3 4.0 - 0.3 0.3 - 0.3 0.3 - 0.3 6.0 - 0.3 4 -20 mA -0.3 4.0 -0.3 6.0 -40 125 °C -40 105 °C -40 150 °C -40 125 °C -55 150 °C -55 150 °C Freescale Semiconductor ...
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... Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESC51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Freescale Semiconductor Table 10-2 56F8014 ESD Protection Min 2000 ...
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... Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 7. See Section 12.1 for more details on thermal design considerations. 94 56F8014 Technical Data, Rev. 11 Freescale Semiconductor ...
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... Flash Data Retention with <100 Program/Erase Cycles Note: Total chip source or sink current cannot exceed 50mA Default Mode Pin Group 1: GPIO, TDI, TDO, TMS, TCK Pin Group 2: RESET, GPIOA7 Pin Group 3: ADC analog inputs Freescale Semiconductor ( 0V, V REFL SSA SS Symbol ...
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... Pull-Up Disabled 56F8014 Technical Data, Rev. 11 Test Typ Max Unit Conditions — — OHmax — 0 OLmax μA 0 +/- 2 2. 5.5V μ -30 -60 0 +/- 2.5 μA 0 +/- 2 2.4V to OUT 5. 0.35 — V — 10 — pF — 10 — pF — 4.0 4.5 5.0 5.5 6.0 Freescale Semiconductor ...
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... Processor Core in STOP state All peripheral module and core clocks are off ADC powered off Voltage Regulator in Standby mode 1. No Output Switching All ports configured as inputs All inputs Low No DC Loads Freescale Semiconductor Typical @ 3.3V, 25°C Conditions I 42mA 17mA 5mA 430μA 300μ ...
Page 98
... Figure 10-2. 56F8014 Technical Data, Rev. 11 Typ Max Unit Min 2.60 2.7 — V 2.05 2.15 — V — 50 — mV — 1.8 1.9 V Table 10-8. Typical Max Unit — 3.6 2.5 2.75 450 650 — 30 Minutes Table 10-5. Unless otherwise specified, Freescale Semiconductor ...
Page 99
... Program time 2 Erase time Mass erase time 1. There is additional overhead which is part of the programming sequence. See the 56F801X Peripheral Reference Manual for details. 2. Specifies page erase time. There are 512 bytes per page in the Program Flash memory. Freescale Semiconductor Low – V )/2 ...
Page 100
... Table 10-11 PLL Timing Symbol f rosc lock t jitterpll 56F8014 Technical Data, Rev Typ Max — — — — 3 — — 3 90% 50% 10 fall rise Min Typ Max — 8 — — 192 — — 40 100 350 Freescale Semiconductor Unit MHz Unit MHz MHz µs ps ...
Page 101
... Output frequency after factory trim. 2. This is the time required from standby to normal mode transition required to meet SCI requirements See Figure 10-5. 8.16 8.08 8 7.92 7.84 -50 -25 Figure 10-5 Relaxation Oscillator Temperature Variation (Typical) After Trim Freescale Semiconductor Symbol Minimum f — — roscs t — jitterrosc ...
Page 102
... Figure 10-6 GPIO Interrupt Timing (Negative Edge-Sensitive) 102 Symbol Typical Min 96T + 64T RDA OSC t — oscillator clock cycle. For an operating frequency of 32MHz 31.25ns. At 8MHz osc T IW 56F8014 Technical Data, Rev. 11 1,2 Typical Max Unit See Figure — ns — ns 10-6 97T + 65T ns OSC 6T ns Freescale Semiconductor ...
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... Disable time (hold time to high-impedance state) Slave Data Valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave Freescale Semiconductor 1 Table 10-14 SPI Timing Symbol Min t C 125 62.5 t ELD — ELG — ...
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... SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) t MISO (Input) MOSI (Output) Figure 10-7 SPI Master Timing (CPHA = 0) 104 SS is held High on master MSB in Bits 14– Master MSB out Bits 14– 56F8014 Technical Data, Rev LSB in (ref Master LSB out t R Freescale Semiconductor ...
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... DV MOSI (Output) Figure 10-8 SPI Master Timing (CPHA = 1) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 10-9 SPI Slave Timing (CPHA = 0) Freescale Semiconductor SS is held High on master MSB in Bits 14– Master MSB out Bits 14– 1 ...
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... Slave MSB out Bits 14– MSB in Bits 14–1 Table 10-15 Timer Timing Symbol Min INHL P 125 OUT P 50 OUTHL 56F8014 Technical Data, Rev ELG Slave LSB out LSB Max Unit See Figure — ns 10-11 — ns 10-11 — ns 10-11 — ns 10-11 Freescale Semiconductor ...
Page 107
... Timer Inputs Timer Outputs Freescale Semiconductor P INHL OUTHL OUT Figure 10-11 Timer Timing 56F8014 Technical Data, Rev. 11 Quad Timer Timing P INHL P OUTHL 107 ...
Page 108
... TOL_SYNCH T 13 BREAK 11 RXD PW Figure 10-12 RXD Pulse Width TXD PW Figure 10-13 TXD Pulse Width 56F8014 Technical Data, Rev Max Unit See Figure (f /16) Mbps — MAX 1.04/BR ns 10-12 1.04/BR ns 10- Master node bit periods Slave node bit periods Freescale Semiconductor ...
Page 109
... LOW period of the SCL signal, it must output the next data bit to the SDA line 1000 + 250 = 1250ns (according to the Standard mode I rmax SU; DAT total capacitance of the one bus line in pF. b Freescale Semiconductor 2 Table 10- Timing Standard Mode Symbol Minimum Maximum f ...
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... SU; STA BR t HIGH Table 10-18 JTAG Timing Symbol Min Max f DC SYS_CLK — — )/2 56F8014 Technical Data, Rev HD; STA SP t SU; STO P 2 Unit See Figure MHz 10-15 — ns 10-15 — ns 10-16 — ns 10- 10- 10- Freescale Semiconductor t BUF S C Bus ...
Page 111
... TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) Figure 10-16 Test Access Port Timing Diagram Freescale Semiconductor t DS Input Data Valid t DV Output Data Valid t TS 56F8014 Technical Data, Rev. 11 JTAG Timing t DH 111 ...
Page 112
... AIC +/- 3 +/- 5 +/- .6 +/- 1 GUARANTEED +/- 4 +/- 9 +/- 6 +/- 12 1.01 to .99 — V REFH — V DDA 0 +/- 2 0 — — 3 Figure 10-17 — Figure 10-17 — 10.0 Freescale Semiconductor Unit Bits MHz V 3 cycles 3 cycles 3 cycles 3 cycles 5 LSB 5 LSB mV mV — μA μ Ohms Bits ...
Page 113
... One aspect of this circuit is that there is an on-going input current, which is a function of the analog input voltage, V and the ADC clock frequency. REF Freescale Semiconductor 10-1. )/2, while the other charges to the analog input voltage. When the REFL 56F8014 Technical Data, Rev. 11 ...
Page 114
... Ohm equiv resistance ESD Resistor 100 Ohms REFHx REFLx 1 × ( ADC Clock Rate ) 1 (ADC Clock Rate 56F8014 Technical Data, Rev Singled Ended Mode Differential Mode Singled Ended Mode Differential Mode + + 100 ohm 125 ohm − × -12 Freescale Semiconductor ...
Page 115
... Sum the total of all arrive at the resistive load contribution to power. Assume V = 0.5 for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW. Freescale Semiconductor 2 *F CMOS power dissipation corresponding to the Intercept 1 ...
Page 116
... In previous discussions, power consumption due to parasitics associated with pure input pins is ignored assumed to be negligible. 116 56F8014 Technical Data, Rev. 11 Freescale Semiconductor ...
Page 117
... ANB0/GPIOC4 ANB1/GPIOC5 ANB2/V /GPIOC6 REFL ANB3/GPIOC7 V DDA Note: Alternate signals are in italic Figure 11-1 Top View, 56F8014 32-Pin LQFP Package Freescale Semiconductor Figure 11-1 shows the package outline for the 32-pin LQFP, ORIENTATION MARK PIN 25 PIN 1 PIN 1 7 PIN 9 56F8014 Technical Data, Rev. 11 ...
Page 118
... PWM5,FAULT2,T3 ANA0 21 GPIOB0 GPIOC0 SCLK/, GPIOA4 SS_IO PWM4/FAULT1/T2 TCK 23 GPIOA2 GPIOD2 RESET 24 GPIOA7 56F8014 Technical Data, Rev Pin No. Signal Name 25 V DD_IO 26 V SS_IO 27 GPIOA1 PWM1 28 GPIOA0 PWM0 29 TDI GPIOD0 30 TMS GPIOD3 31 TDO PWM2 GPIOD1 V 32 GPIOB6 CAP RXD,SDA,CLKIN Freescale Semiconductor ...
Page 119
... B B1 DETAIL –AB– SEATING –AC– PLANE 0.10 (0.004 DETAIL AD Figure 11-2 56F8014 32-Pin LQFP Mechanical Information Freescale Semiconductor 4X 0.20 (0.008) AB T– –U– –Z– 0.20 (0.008) AC T–U Z DETAIL AD BASE METAL N É É É É É É ...
Page 120
... (Ψ where : T = Thermocouple temperature on top of package ( T 120 , can be obtained from the equation C/W) . For instance, the user can change the size of the heat θCA ) can be used to determine the junction temperature with 56F8014 Technical Data, Rev. 11 Freescale Semiconductor ...
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... DD SS tolerances. • Ensure that capacitor leads and associated printed circuit traces that connect to the chip V pins are as short as possible • Bypass the V and Freescale Semiconductor o C/W) CAUTION of any voltages (GND) pin /V Ceramic and tantalum capacitors tend to provide better DDA SSA. ...
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... Because the Flash memory is programmed through the JTAG/EOnCE port, SPI, SCI or I should provide an interface to this port if in-circuit Flash programming is desired. 122 , V and V REF DDA and V and separate ground planes for V DD DDA 56F8014 Technical Data, Rev. 11 pins SSA and SSA and V traces. DDA SSA 2 C, the designer Freescale Semiconductor ...
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... COPTO COP_TOUT CNTR COPCTR COP_CNTR 56F8014 Technical Data, Rev. 11 Electrical Design Considerations Abient Temperature Order Number (MHz) Range 32 -40° 105° C MC56F8014VFAE* 32 –40° to +125 °C MC56F8014MFAE* Data Sheet Processor Expert Legacy Acronym Acronym ADC_ADCR1 ADC_ADCR1 ADC_ADCR2 ADC_ADCR2 ADC_ADZCC ADC_ADZCC ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® ...