R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 100
R5F21162SP#U0
Manufacturer Part Number
R5F21162SP#U0
Description
IC R8C MCU FLASH 8K 20SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/16r
Datasheets
1.R5F211A2SPU0.pdf
(300 pages)
2.R5F21173DSPU0.pdf
(40 pages)
3.R5F21173DSPU0.pdf
(281 pages)
Specifications of R5F21162SP#U0
Core Processor
R8C
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SIO, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-SSOP
For Use With
R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
Figure 13.2
Timer X Mode Register
b7 b6 b5 b4
NOTES :
1.
2. Refer to 20.4.2 Tim er X for precautions on the TXS bit.
The IR bit in the INT1IC register may be set to “1” (requests interrupt) w hen the R0EDG bit is rew ritten.
Refer to 20.2.5 Changing Interrupt Factor.
Jan 19, 2006
b3 b2
b1 b0
TXMR Register
Bit Symbol
TXMOD0
TXMOD1
TXOCNT
TXMOD2
Symbol
R0EDG
TXEDG
TXUND
TXMR
TXS
Page 85 of 254
Operating Mode Select Bit 0, 1
_____
INT1
Polarity Sw itch Bit
Timer X Count Start Flag
P3_7/CNTR0
Operating Mode Select Bit 2
Active Edge Reception Flag
Timer X Underflow Flag
/CNTR0 Signal
________
Address
Bit Name
008Bh
Select Bit
(1)
(2)
b1 b0
0 0 : Timer mode or pulse period measurement
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse w idth measurement mode
Function varies depending on operating mode
0 : Stops counting
1 : Starts counting
Function varies depending on operating mode
0 : Other than pulse period measurement mode
1 : Pulse period measurement mode
Function varies depending on operating mode
Function varies depending on operating mode
mode
After Reset
Function
00h
13. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW
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