S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 318

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime
Module Base + 0x0018 to Module Base + 0x001B
1. Read: Anytime
Module Base + 0x0010 to Module Base + 0x0013
Freescale’s Scalable Controller Area Network (S12MSCANV3)
11.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see
“Identifier Registers
“Identifier Acceptance
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only
the first two (CANIDAR0/1, CANIDMR0/1) are applied.
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
318
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
AC[7:0]
Field
7-0
Figure 11-21. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7
Figure 11-20. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3
Reset
Reset
W
R
W
R
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
AC7
AC7
0
7
0
7
(IDR0–IDR3)”) of incoming messages in a bit by bit manner (see
Table 11-22. CANIDAR0–CANIDAR3 Register Field Descriptions
Filter”).
AC6
AC6
0
6
0
6
S12XS Family Reference Manual, Rev. 1.11
AC5
AC5
0
5
5
0
AC4
AC4
0
4
Description
0
4
AC3
AC3
0
3
3
0
AC2
AC2
0
2
0
2
Access: User read/write
Freescale Semiconductor
Access: User read/write
Section 11.3.3.1,
AC1
Section 11.4.3,
AC1
0
1
1
0
AC0
AC0
0
0
0
0
(1)
(1)