R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 115

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 86 of 573
8.
The bus cycles differ when accessing ROM, RAM, DTC vector area, DTC control data and when accessing SFR.
Table 8.1 lists Bus Cycles by Access Area of R8C/32C Group.
ROM, RAM, DTC vector area, DTC control data and SFR are connected to the CPU by an 8-bit bus. When accessing
in word (16-bit) units, these areas are accessed twice in 8-bit units.
Table 8.2 shows Access Units and Bus Operations.
Table 8.1
Table 8.2
SFR/Data flash
Program ROM/RAM
Bus
Even address
Even address
Odd address
Word access
Word access
Odd address
Byte access
Byte access
Area
Bus Cycles by Access Area of R8C/32C Group
Access Units and Bus Operations
Access Area
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
SFR, Data flash
Even
Odd
Data
Data
Even
Odd
2 cycles of CPU clock
1 cycle of CPU clock
Even + 1
Odd + 1
Data
Data
Data
Data
Bus Cycle
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
DTC vector area, DTC control data
ROM (program ROM), RAM,
Even
Even
Odd
Odd
Data
Data
Data
Data
Even + 1
Odd + 1
Data
Data
8. Bus