R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 142

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 113 of 573
Figure 9.8
Stop mode
Interrupt request generation
9.7.3.3
(flash memory operates)
(flash memory stops)
The MCU exits stop mode by a reset or peripheral function interrupt.
Figure 9.8 shows the Time from Stop Mode to Interrupt Routine Execution.
To use a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit to 1.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for
(2) Set the I flag to 1.
(3) Operate the peripheral function to be used for exiting stop mode.
The clock used immediately before stop mode divided by 8 is used as the CPU clock when the MCU exits stop
mode by a peripheral function interrupt. To enter stop mode, set the CM35 bit in the CM3 register to 0 (settings
of CM06 bit in CM0 register and bits CM16 and CM17 in CM1 register enabled)
FMR0 Register
FMSTP Bit
exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for
exiting stop mode to 000b (interrupt disabled).
When the MCU exits stop mode by a peripheral function interrupt, the interrupt sequence is executed when
an interrupt request is generated and the CPU clock supply starts.
0
1
stabilization time
100 ms (max.)
Internal power
Exiting Stop Mode
Time from Stop Mode to Interrupt Routine Execution
T0
Oscillation time of CPU clock
Stabilization Time (T0)
source used immediately
before stop mode
Internal Power
100 µs (max.)
100 µs (max.)
T1
Period of system clock
Period of system clock
activation sequence
× 1 cycle + 60 µs
Activation (T2)
Flash Memory
Flash memory
Time until
× 1 cycle
(max.)
T2
Period of CPU clock
restart sequence
Same as above
Supply (T3)
CPU Clock
× 2 cycles
CPU clock
Time until
T3
Period of CPU clock
Interrupt sequence
Same as above
Sequence (T4)
× 20 cycles
Time for
Interrupt
9. Clock Generation Circuit
T4
The total of T0
to T4 is the time
from wait mode to
interrupt routine
execution.
Remarks