R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 20

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

26.
27.
25.3
25.4
25.5
25.6
25.7
25.8
25.9
26.1
26.2
26.3
26.4
26.5
26.6
27.1
27.2
25.2.3
25.2.4
25.2.5
25.2.6
25.2.7
25.2.8
25.2.9
25.2.10 IIC bus Status Register (ICSR) ......................................................................................................... 401
25.2.11 Slave Address Register (SAR) .......................................................................................................... 402
25.2.12 IIC bus Shift Register (ICDRS) ........................................................................................................ 402
25.3.1
25.3.2
25.3.3
25.4.1
25.4.2
25.4.3
25.4.4
25.4.5
25.5.1
25.5.2
25.5.3
26.3.1
26.3.2
26.3.3
26.4.1
26.4.2
26.4.3
26.4.4
27.2.1
27.2.2
Hardware LIN .............................................................................................................................. 428
A/D Converter ............................................................................................................................. 443
Common Items for Multiple Modes ...................................................................................................... 403
I
Clock Synchronous Serial Mode ........................................................................................................... 418
Examples of Register Setting ................................................................................................................ 421
Noise Canceller ..................................................................................................................................... 425
Bit Synchronization Circuit ................................................................................................................... 426
Notes on I
Overview ............................................................................................................................................... 428
Input/Output Pins .................................................................................................................................. 429
Registers ................................................................................................................................................ 430
Function Description ............................................................................................................................. 432
Interrupt Requests .................................................................................................................................. 441
Notes on Hardware LIN ........................................................................................................................ 442
Overview ............................................................................................................................................... 443
Registers ................................................................................................................................................ 445
2
C bus Interface Mode ......................................................................................................................... 407
I/O Function Pin Select Register (PINSR) ....................................................................................... 395
IIC bus Transmit Data Register (ICDRT) ......................................................................................... 396
IIC bus Receive Data Register (ICDRR) .......................................................................................... 396
IIC bus Control Register 1 (ICCR1) ................................................................................................. 397
IIC bus Control Register 2 (ICCR2) ................................................................................................. 398
IIC bus Mode Register (ICMR) ........................................................................................................ 399
IIC bus Interrupt Enable Register (ICIER) ....................................................................................... 400
Transfer Clock .................................................................................................................................. 403
SDA Pin Digital Delay Selection ...................................................................................................... 405
Interrupt Requests ............................................................................................................................. 406
I2C bus Format ................................................................................................................................. 407
Master Transmit Operation ............................................................................................................... 408
Master Receive Operation ................................................................................................................ 410
Slave Transmit Operation ................................................................................................................. 413
Slave Receive Operation ................................................................................................................... 416
Clock Synchronous Serial Format .................................................................................................... 418
Transmit Operation ........................................................................................................................... 419
Receive Operation ............................................................................................................................. 420
LIN Control Register 2 (LINCR2) .................................................................................................... 430
LIN Control Register (LINCR) ......................................................................................................... 431
LIN Status Register (LINST) ............................................................................................................ 431
Master Mode ..................................................................................................................................... 432
Slave Mode ....................................................................................................................................... 435
Bus Collision Detection Function ..................................................................................................... 439
Hardware LIN End Processing ......................................................................................................... 440
On-Chip Reference Voltage Control Register (OCVREFCR) ......................................................... 445
A/D Register i (ADi) (i = 0 to 7) ...................................................................................................... 446
2
C bus Interface .................................................................................................................... 427
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