R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 206

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 177 of 573
Figure 15.5
Figure 15.6
Note:
Note:
DTC activation source generation
DTC activation source generation
(writing the transmit data register
(Reading the receive data register
1. When the DTC activation source is SSU/I
1. When the DTC activation source is SSU/I
Instead, writing data to the transmit data register during DTC data transfer sets the TDRE bit to 0.
Instead, reading the receive data register during DTC data transfer sets the RDRF bit to 0.
sets the TDRE bit to 0)
sets the RDRF bit to 0)
Write back control data
Write back control data
Read control data
Read control data
Read DTC vector
Read DTC vector
Transfer data
Transfer data
NMIF = 1?
NMIF = 1?
CHNE=1?
CHNE=1?
Branch 1
Branch 1
End
End
No
No
No
No
Receive Data Full
Transmit Data Empty
DTC Internal Operation Flowchart When DTC Activation Source is SSU/I
DTC Internal Operation Flowchart When DTC Activation Source is SSU/I
(1)
(1)
Yes
Yes
Yes
Yes
(writing the transmit data register
2
(Reading the receive data register
2
C bus receive data full, the DTC does not set the RDRF bit in the SSSR register/the ICSR register to 0.
C bus transmit data empty, the DTC does not set the TDRE bit in the SSSR register/the ICSR register to 0.
sets the TDRE bit to 0)
sets the RDRF bit to 0)
Write back control data
Write back control data
Read control data
Read control data
Transfer data
Transfer data
CHNE=1?
CHNE=1?
No
No
(1)
(1)
Branch 1
0 is written to the bit among bits DTCENi0 to DTCENi1, DTCENi3 to DTCENi7 and an interrupt request is
generated when transfer is either of the following:
- Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode
- Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in repeat mode
Branch 1
0 is written to the bit among bits DTCENi0 to DTCENi1, DTCENi3 to DTCENi7 when transfer is either of the
following:
- Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode
- Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in repeat mode
DTCENi0 to DTCENi1, DTCENi3 to DTCENi7: Bits in DTCENi (i = 0 to 3, 5, 6) registers
RPTINT, CHNE: Bits in DTCCRj registers
NMIF: Bit in DTCTL register
RDRF: Bit in SSSR/ICSR register
DTCENi0 to DTCENi1, DTCENi3 to DTCENi7: Bits in DTCENi (i = 0 to 3, 5, 6) registers
RPTINT, CHNE: Bits in DTCCRj registers
NMIF: Bit in DTCTL register
TDRE: Bit in SSSR/ICSR register
Yes
Yes
(Reading the receive data register
(writing the transmit data register
does not set the RDRF bit to 0)
Generate an interrupt request
sets the TDRE bit to 0)
Write 0 to the bit among
Write 0 to the bit among
DTCENi0 to DTCENi1,
Write back control data
DTCENi0 to DTCENi1,
Write back control data
DTCENi3 to DTCENi7
DTCENi3 to DTCENi7
Interrupt handling
Transfer data
Transfer data
for the CPU
CHNE=1?
CHNE=1?
No
No
(1)
Yes
Yes
(Reading the receive data register
(writing the transmit data register
does not set the RDRF bit to 0)
sets the TDRE bit to 0)
Write back control data
Write back control data
Read control data
Read control data
Transfer data
Transfer data
CHNE=1?
CHNE=1?
No
No
2
2
C bus
C bus
(1)
Yes
Yes
15. DTC