R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 270

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 241 of 573
Figure 19.5
19.3.3
(or TRCTRG input signal)
Input signal after passing
TRCIOj input signal
signal)
(or TRCTRG input
fOCO40M
TRCIOj input signal
TRCCLK
through digital filter
fOCO-F
The input to TRCTRG or TRCIOj (j = A, B, C, or D) is sampled, and the level is considered to be determined
when three matches occur. The digital filter function and sampling clock are selected using the TRCDF register.
Figure 19.5 shows a Digital Filter Block Diagram.
Sampling clock
f32
f1
f2
f4
f8
Digital Filter
TCK0 to TCK2: Bits in TRCCR1 register
DFTRG, DFCK0 to DFCK1, DFj: Bits in TRCDF register
IOA0 to IOA2, IOB0 to IOB2: Bits in TRCIOR0 register
IOC0 to IOC2, IOD0 to IOD2: Bits in TRCIOR1 register
TCEG1 to TCEG0: Bits in TRCCR2 register
j = A, B, C, or D
Clock cycle selected by
= 011b
Digital Filter Block Diagram
= 100b
Timer RC operation clock
(or DFCK1 to DFCK0)
= 010b
= 101b
TCK2 to TCK0
f1 or fOCO40M
D
D
= 001b
= 110b
Latch
Latch
C
TCK2 to TCK0
C
= 111b
Q
Q
= 000b
Count source
D
f32
f8
f1
Latch
C
= 01b
= 10b
If fewer than three matches occur,
the matches are treated as noise
and no transmission is performed.
= 00b
DFCK1 to DFCK0
= 11b
Q
D
Latch
C
Sampling clock
Q
D
Latch
C
Q
Match detect
Maximum signal transmission
circuit
delay is five sampling clock
Three matches occur and a
signal change is confirmed.
pulses.
DFj (or DFTRG)
1
0
(or TCEG1 to TCEG0)
IOA2 to IOA0
IOB2 to IOB0
IOC2 to IOC0
IOD2 to IOD0
Edge detect
circuit
19. Timer RC