R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 287

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 258 of 573
19.6
Table 19.11
j = B, C, or D
h = A, B, C, or D
Count source
Count operation
PWM waveform
Count start condition
Count stop condition
Interrupt request generation
timing
TRCIOA pin function
TRCIOB, TRCIOC, and
TRCIOD pin functions
INT0 pin function
Read from timer
Write to timer
Select functions
This mode outputs PWM waveforms. A maximum of three PWM waveforms with the same period are output.
The PWM mode, or the timer mode, can be selected for each individual pin. (However, since the TRCGRA register
is used when using any pin for the PWM mode, the TRCGRA register cannot be used for the timer mode.)
Table 19.11 lists the Specifications of PWM Mode, Figure 19.13 shows a PWM Mode Block Diagram, Table 19.12
lists the Functions of TRCGRh Register in PWM Mode, and Figures 19.14 and 19.15 show Operating Examples of
PWM Mode.
PWM Mode
Item
Specifications of PWM Mode
f1, f2, f4, f8, f32, fOCO40M, fOCO-F
External signal (rising edge) input to TRCCLK pin
Increment
PWM period: 1/fk × (m + 1)
Active level width: 1/fk × (m - n)
Inactive width: 1/fk × (n + 1)
1 (count starts) is written to the TSTART bit in the TRCMR register.
• When the CSEL bit in the TRCCR2 register is set to 0 (count continues
• When the CSEL bit in the TRCCR2 register is set to 1 (count stops at
• Compare match (contents of registers TRC and TRCGRh match)
• The TRC register overflows.
Programmable I/O port
Programmable I/O port or PWM output (selectable individually for each
pin)
Programmable I/O port, pulse output forced cutoff signal input, or INT0
interrupt input
The count value can be read by reading the TRC register.
The TRC register can be written to.
• One to three pins selectable as PWM output pins
• Active level selectable for each pin
• Initial level selectable for each pin
• Buffer operation (Refer to 19.3.2 Buffer Operation .)
• Pulse output forced cutoff signal input (Refer to 19.3.4 Forced Cutoff
• A/D trigger generation
after compare match with TRCGRA).
0 (count stops) is written to the TSTART bit in the TRCMR register.
PWM output pin retains output level before count stops, TRC register
retains value before count stops.
compare match with TRCGRA register).
The count stops at the compare match with the TRCGRA register. The
PWM output pin retains the level after the output is changed by the
compare match.
One or more of pins TRCIOB, TRCIOC, and TRCIOD
of Pulse Output .)
fk: Count source frequency
m: TRCGRA register setting value
n: TRCGRj register setting value
n+1
m+1
m-n
Specification
(“L” is active level)
19. Timer RC