R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 289

MCU 1KB FLASH 16K ROM 20-LSSOP

R5F21324CNSP#U0

Manufacturer Part Number
R5F21324CNSP#U0
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Cr
Datasheet

Specifications of R5F21324CNSP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 260 of 573
19.6.1
Notes:
19.6.2
Notes:
After Reset
1. Set to these bits when the TSTART bit in the TRCMR register is set to 0 (count stops).
2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the
3. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.
After Reset
1. Enabled when in PWM mode.
2. Enabled when in output compare function, PWM mode, or PWM2 mode. For notes on PWM2 mode, refer to
3. Enabled when in PWM2 mode.
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0121h
Address 0130h
TRCCR1 register is set.
19.9.6 TRCMR Register in PWM2 Mode.
Symbol
Symbol TCEG1
Symbol
Symbol
TCEG0 TRCTRG input edge select bit
TCEG1
Bit
CCLR
Bit
POLB
POLC
POLD
TCK0
TCK1
TCK2
CSEL
TOA
TOB
TOC
TOD
Timer RC Control Register 1 (TRCCR1) in PWM Mode
Timer RC Control Register 2 (TRCCR2) in PWM Mode
CCLR
b7
b7
0
0
TRCIOA output level select bit
TRCIOB output level select bit
TRCIOC output level select bit
TRCIOD output level select bit
Count source select bit
TRC counter clear select bit
PWM mode output level control
bit B
PWM mode output level control
bit C
PWM mode output level control
bit D
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
TRC count operation select bit
(1)
(1)
(1)
TCEG0
TCK2
b6
b6
0
0
Bit Name
Bit Name
TCK1
CSEL
b5
b5
0
0
(1)
TCK0
b4
b4
(1)
(3)
(1, 2)
(2)
(1, 2)
(1, 2)
0
1
0: TRCIOB output level selected as “L” active
1: TRCIOB output level selected as “H” active
0: TRCIOC output level selected as “L” active
1: TRCIOC output level selected as “H” active
0: TRCIOD output level selected as “L” active
1: TRCIOD output level selected as “H” active
0: Count continues at compare match with the
1: Count stops at compare match with the TRCGRA
b7 b6
0 0: Disable the trigger input from the TRCTRG pin
0 1: Rising edge selected
1 0: Falling edge selected
1 1: Both edges selected
Disabled in PWM mode
0: Initial output selected as non-active level
1: Initial output selected as active level
b6 b5 b4
0: Disable clear (free-running operation)
1: Clear by compare match in the TRCGRA register
0 0 0: f1
0 0 1: f2
0 1 0: f4
0 1 1: f8
1 0 0: f32
1 0 1: TRCCLK input rising edge
1 1 0: fOCO40M
1 1 1: fOCO-F
TRCGRA register
register
TOD
b3
b3
0
1
POLD
TOC
b2
b2
0
0
(3)
Function
Function
POLC
TOB
b1
b1
0
0
POLB
TOA
b0
b0
0
0
19. Timer RC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

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