R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 326

MCU 1KB FLASH 16K ROM 20-LSSOP

R5F21324CNSP#U0

Manufacturer Part Number
R5F21324CNSP#U0
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Cr
Datasheet

Specifications of R5F21324CNSP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 297 of 573
21.2.4
Note:
21.2.5
Notes:
After Reset
1. If the BRG count source is switched, set the U0BRG register again.
After Reset
1. The RI bit is set to 0 when the higher byte of the U0RB register is read.
2. In UART mode, set the U0RRM bit to 0 (continuous receive mode disabled).
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 00A4h
Address 00A5h
Symbol UFORM
Symbol
UFORM Transfer format select bit
U0RRM UART0 continuous receive mode
Symbol
CKPOL CLK polarity select bit
Symbol
TXEPT
U0IRS
Bit
Bit
CLK0
CLK1
NCH
UART0 Transmit/Receive Control Register 0 (U0C0)
UART0 Transmit/Receive Control Register 1 (U0C1)
RE
TE
RI
TI
b7
b7
0
0
BRG count source select bit
Reserved bit
Transmit register empty flag
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Data output select bit
Transmit enable bit
Transmit buffer empty flag
Receive enable bit
Receive complete flag
UART0 transmit interrupt source
select bit
enable bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
CKPOL
b6
b6
0
0
(2)
Bit Name
Bit Name
U0RRM
NCH
b5
b5
0
0
(1)
U0IRS
(1)
b4
b4
0
0
b1 b0
Set to 0.
0: Data present in the transmit register
1: No data in the transmit register
0: TXD0 pin set to CMOS output
1: TXD0 pin set to N-channel open-drain output
0: Transmit data output at the falling edge and receive
1: Transmit data output at the rising edge and receive
0: LSB first
1: MSB first
0 0: f1 selected
0 1: f8 selected
1 0: f32 selected
1 1: fC selected
(transmission in progress)
(transmission completed)
data input at the rising edge of the transfer clock
data input at the falling edge of the transfer clock
0: Transmission disabled
1: Transmission enabled
0: Data present in the U0TB register
1: No data in the U0TB register
0: Reception disabled
1: Reception enabled
0: No data in the U0RB register
1: Data present in the U0RB register
0: Transmission buffer empty (TI = 1)
1: Transmission completed (TXEPT = 1)
0: Continuous receive mode disabled
1: Continuous receive mode enabled
TXEPT
b3
b3
RI
1
0
RE
b2
b2
0
0
Function
Function
CLK1
b1
b1
TI
0
1
21. Serial Interface (UART0)
CLK0
TE
b0
b0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R

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