R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 367

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 338 of 573
Figure 22.9
22.4.2
22.4.3
If communication is aborted or a communication error occurs while transmitting or receiving in UART mode,
follow the procedures below:
(1) Set the TE bit in the U2C1 register to 0 (transmission disabled) and the RE bit to 0 (reception disabled).
(2) Set bits SMD2 to SMD0 in the U2MR register to 000b (serial interface disabled).
(3) Set bits SMD2 to SMD0 in the U2MR register to 100b (UART mode, transfer data 7 bits long), 101b
(4) Set the TE bit in the U2C1 register to 1 (transmission enabled) and the RE bit to 1 (reception enabled).
As shown in Figure 22.9, use the UFORM bit in the U2C0 register to select the transfer format. This function is
enabled when transfer data is 8 bits long. Figure 22.9 shows the Transfer Format.
(UART mode, transfer data 8 bits long), or 110b (UART mode, transfer data 9 bits long).
Measure for Dealing with Communication Errors
LSB First/MSB First Select Function
(1) UFORM Bit in U2C0 Register = 0 (LSB first)
(2) UFORM Bit in U2C0 Register = 1 (MSB first)
Transfer Format
The above applies when:
CLK2
TXD2
RXD2
CLK2
TXD2
RXD2
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and
• U2LCH bit in U2C1 register = 0 (not inverted)
• STPS bit in U2MR register = 0 (one stop bit)
• PRYE bit in U2MR register = 1 (parity enabled)
receive data input at the rising edge of the transfer clock)
ST
ST
ST
ST
D0
D0
D7
D7
D1
D1
D6
D6
D2
D2
D5
D5
D3
D3
D4
D4
D4
D4
D3
D3
D5
D5
D2
D2
D6
D6
D1
D1
D7
D7
D0
D0
ST: Start bit
P: Parity bit
SP: Stop bit
P
P
P
P
22. Serial Interface (UART2)
SP
SP
SP
SP