R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 369

MCU 1KB FLASH 16K ROM 20-LSSOP

R5F21324CNSP#U0

Manufacturer Part Number
R5F21324CNSP#U0
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Cr
Datasheet

Specifications of R5F21324CNSP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 340 of 573
Figure 22.12
22.4.6
22.4.7
input signal
Sampling
The CTS function is used to start transmit operation when “L” is applied to the CTS2/RTS2 pin. Transmit
operation begins when the CTS2/RTS2 pin is held low. If the “L” signal is switched to “H” during transmit
operation, the operation stops after the ongoing transmit/receive operation is completed.
When the RTS function is used, the CTS2/RTS2 pin outputs “L” when the MCU is ready for a receive
operation. The output level goes high at the first falling edge of the CLK2 pin.
• The CRD bit in the U2C0 register = 1 (CTS/RTS function disabled)
• The CRD bit = 0, CRS bit = 0 (CTS function selected)
• The CRD bit = 0, CRS bit = 1 (RTS function selected)
When the DF2EN bit in the URXDF register is set to 1 (RXD2 digital filer enabled), the RXD2 input signal is
loaded internally via the digital filter circuit for noise reduction. The noise canceller consists of three cascaded
latch circuits and a match detection circuit. The RXD2 input signal is sampled on the internal basic clock with a
frequency 16 times the bit rate. It is recognized as a signal and the level is passed forward to the next circuit
when three latch outputs match. When the outputs do not match, the previous value is retained.
In other words, when the level is changed within three clocks, the change is recognized as not a signal but noise.
Figure 22.12 shows a Block Diagram of RXD2 Digital Filter Circuit.
RXD2
clock
The CTS2/RTS2 pin operates as the programmable I/O function.
The CTS2/RTS2 pin operates as the CTS function.
The CTS2/RTS2 pin operates as the RTS function.
CTS/RTS Function
RXD2 Digital Filter Select Function
Note:
Internal basic clock
1. When the CKDIR bit in the U2MR register is 0 (internal clock), the internal basic clock is set to fj/(n+1)
Block Diagram of RXD2 Digital Filter Circuit
Sampling clock
D
(fj = f1, f8, f32, fC; n = setting value in the U2BRG register).
When the CKDIR bit in the U2MR register is 1 (external clock), the internal basic clock is set to fEXT/(n+1)
(fEXT is input from the CLK2 pin. n = setting value in the U2BRG register).
period
Latch
C
(1)
Q
D
Latch
C
Q
D
Latch
C
Q
detection
Match
circuit
(DF2EN bit)
URXDF
register
22. Serial Interface (UART2)
Internal RXD2
input signal

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