R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 394

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 365 of 573
24.2.5
Notes:
24.2.6
Notes:
b15 to b0
After Reset
After Reset
1. The SSRDR register retains the data received before an overrun error occurs (ORER bit in the SSSR register set
2. When the SSU data transfer length is set to 9 bits or more with the SSBR register, access the SSRDR register in
After Reset
1. The set clock is used when the MSS bit is set to 1 (operates as master device).
2. The SSCK pin functions as the transfer clock output pin when the MSS bit is set to 1 (operates as master
3. The RSSTP bit is disabled when the MSS bit is set to 0 (operates as slave device).
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
Address 0197h to 0196h
Address 0198h
to 1 (overrun error)). When an overrun error occurs, the receive data may contain errors and therefore should be
discarded.
16-bit units.
device). The MSS bit is set to 0 (operates as slave device) when the CE bit in the SSSR register is set to 1
(conflict error occurs).
Symbol
Symbol
Symbol
Symbol
RSSTP Receive single stop bit
Bit
Bit
Bit
CKS0
CKS1
CKS2
MSS
SS Receive Data Register (SSRDR)
SS Control Register H (SSCRH)
Symbol
—
—
—
—
b15
b7
b7
—
—
—
1
1
0
Transfer clock select bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Master/slave device select bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Store the receive data.
The receive data is transferred to the SSRDR register and the receive operation is
completed when 1 byte of data has been received by the SSTRSR register. At this time,
the next receive operation is possible.
Continuous reception is possible using registers SSTRSR and SSRDR.
RSSTP
b14
b6
b6
—
—
1
1
0
Bit Name
MSS
b13
b5
—
—
b5
1
1
0
(3)
(1)
(1, 2)
b12
(2)
b4
b4
—
—
—
1
1
0
b2 b1 b0
0: Operates as slave device
1: Operates as master device
0: Maintains receive operation after receiving 1 byte of
1: Completes receive operation after receiving 1 byte
0 0 0: f1/256
0 0 1: f1/128
0 1 0: f1/64
0 1 1: f1/32
1 0 0: f1/16
1 0 1: f1/8
1 1 0: f1/4
1 1 1: Do not set.
data
of data
b11
b3
b3
—
—
—
Function
1
1
0
24. Synchronous Serial Communication Unit (SSU)
CKS2
b10
b2
b2
—
—
1
1
0
Function
CKS1
b1
b9
b1
—
—
1
1
0
CKS0
b0
b8
b0
—
—
1
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
R