R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 409

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 380 of 573
Figure 24.8
(1)
(2)
(3)
(4)
(5)
(6)
(7)
SSCRH register
SSCRH register
SSER register
Mode)
Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Read receive data in SSRDR register
Read receive data in SSRDR register
Read ORER bit in SSSR register
Read ORER bit in SSSR register
Read RDRF bit in SSSR register
Dummy read of SSRDR register
Read RDRF in SSSR register
No
No
ORER = 1 ?
ORER = 1 ?
Initialization
RDRF = 1 ?
RDRF = 1 ?
received?
Last data
Start
End
RSSTP bit ← 1
RSSTP bit ← 0
RE bit ← 0
No
No
Yes
No
Yes
Yes
Yes
Yes
processing
Overrun
error
24. Synchronous Serial Communication Unit (SSU)
(3) If a receive error occurs, perform error
(6) processing after reading the ORER bit. Then set
(1) After setting each register in the synchronous serial
(2) Determine whether it is the last 1 byte of data to be
(4) Confirm that the RDRF bit is set to 1. If the RDRF
(5) Before the last 1 byte of data is received, set the
(7) Confirm that the RDRF bit is set to 1. When the
the ORER bit to 0. Transmission/reception cannot
be restarted while the ORER bit is set to 1.
communication unit register, a dummy read of the
SSRDR register is performed and the receive
operation is started.
received. If so, set to stop after the data is received.
bit is set to 1, read the receive data in the SSRDR
register. When the SSRDR register is read, the
RDRF bit is automatically set to 0.
RSSTP bit to 1 and stop after the data is
received.
receive operation is completed, set the RSSTP bit to
0 and the RE bit to 0 before reading the last 1 byte
of data. If the SSRDR register is read before setting
the RE bit to 0, the receive operation is restarted
again.