R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 411

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 382 of 573
Figure 24.9
Note:
(4)
(5)
(1)
(2)
(3)
(6)
1. Write 0 after reading 1 to set the TEND bit to 0.
SSSR register
SSER register
Communication Mode)
Sample Flowchart of Data Transmission/Reception (Clock Synchronous
Write transmit data to SSTDR register
Read receive data in SSRDR register
Read TDRE bit in SSSR register
Read RDRF bit in SSSR register
Read TEND bit in SSSR register
No
transmission
RDRF = 1 ?
TEND = 1 ?
Initialization
TDRE = 1 ?
continues?
Start
Data
End
TEND bit ← 0
RE bit ← 0
TE bit ← 0
Yes
Yes
No
Yes
(2)
No
No
Yes
(1)
24. Synchronous Serial Communication Unit (SSU)
(2) Confirm that the RDRF bit is set to 1. If the RDRF
(3) Determine whether the data transmission
(4) When the data transmission is completed, the
(5) Set the TEND bit to 0 and bits RE and TE in
(6) the SSER register to 0 before ending transmit/
(1) After reading the SSSR register and confirming
bit is set to 1, read the receive data in the SSRDR
register. When the SSRDR register is read, the
RDRF bit is automatically set to 0.
continues
TEND bit in the SSSR register is set to 1.
that the TDRE bit is set to 1, write the transmit
data to the SSTDR register. When the transmit
data is written to the SSTDR register, the TDRE
bit is automatically set to 0.
receive mode.