R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 436

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 407 of 573
25.4
Figure 25.4
25.4.1
(1) I
(2) I
Legend:
S
SLA
R/W
A
DATA : Transmit/receive data
P
(a) I
(b) I
2
2
C bus format
C bus timing
When the FS bit in the SAR register is set to 0, the I
Figure 25.4 shows the I
8 bits.
: Start condition
: Slave address
: Indicates the direction of data transmission/reception
: Acknowledge
: Stop condition
2
2
I
C bus format (FS = 0)
C bus format When Start Condition is Retransmitted (FS = 0)
The master device changes the SDA signal from “H” to “L” while the SCL signal is held “H”.
Data is transmitted when:
R/W value is 1: From the slave device to the master device
R/W value is 0: From the master device to the slave device
The receive device sets the SDA signal to “L”.
The master device changes the SDA signal from “L” to “H” while the SCL signal is held “H”.
2
SDA
SCL
C bus Interface Mode
S
1
S
1
I
2
C bus Format
S
I
2
C bus Format and Bus Timing
SLA
SLA
7
7
1 to 7
SLA
1
1
R/W
2
R/W
8
C bus Format and Bus Timing. The first frame following the start condition consists of
1
R/W
1
A
A
1
1
9
A
DATA
DATA
n
n1
1 to 7
m1
DATA
8
A
1
m
A/A
1
2
9
C bus format is used for communication.
A
S
1
A/A
1 to 7
1
SLA
7
P
1
DATA
1
8
Upper: Number of transfer bits (n1, n2 = 1 to 8)
Lower: Number of transfer frames (m1, m2 = 1 or more)
Number of transfer bits (n = 1 to 8)
Number of transfer frames (m = 1 or more)
R/W
1
9
A
A
1
P
DATA
n2
25. I
m2
2
C bus Interface
A/A
1
P
1