R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 448

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 419 of 573
Figure 25.14
25.5.2
In transmit mode, transmit data is output from the SDA pin in synchronization with the falling edge of the
transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when
the MST bit is set to 0.
Figure 25.14 shows the Operating Timing in Transmit Mode (Clock Synchronous Serial Mode).
The transmit procedure and operation in transmit mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Then set bits CKS0 to CKS3 in the
(2) Set the TRS bit in the ICCR1 register to 1 to select transmit mode. This will set the TDRE bit in the ICSR
(3) After confirming that the TDRE bit is set to 1, write transmit data to the ICDRT register. Data is transferred
Program processing
TDRE bit in ICSR
ICCR1 register and the MST bit (initial setting).
register is to 1.
from registers ICDRT to ICDRS and the TDRE bit is automatically set to 1. Continuous transmission is
enabled by writing data to the ICDRT register every time the TDRE bit is set to 1. To switch from transmit
to receive mode, set the TRS bit to 0 while the TDRE bit is set to 1.
TRS bit in ICCR1
ICDRT register
ICDRS register
Transmit Operation
(output)
Operating Timing in Transmit Mode (Clock Synchronous Serial Mode)
register
register
SDA
SCL
(2) Set TRS bit to 1.
(3) Write data to
ICDRT register.
Data 1
b0
Data 1
1
b1
(3) Write data to
2
ICDRT register.
b6
Data 2
7
b7
8
b0
Data 2
1
(3) Write data to
b6
ICDRT register.
7
b7
8
(3) Write data to
Data 3
Data 3
ICDRT register.
25. I
b0
2
1
C bus Interface