R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 454

MCU 1KB FLASH 16K ROM 20-LSSOP

R5F21324CNSP#U0

Manufacturer Part Number
R5F21324CNSP#U0
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Cr
Datasheet

Specifications of R5F21324CNSP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 425 of 573
25.7
Figure 25.20
The states of pins SCL and SDA are routed through the noise canceller before being latched internally.
Figure 25.20 shows a Noise Canceller Block Diagram.
The noise canceller consists of two cascaded latch and match detector circuits. When the SCL pin input signal (or
SDA pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next circuit.
When they do not match, the former value is retained.
f1 (sampling clock)
Noise Canceller
SCL or SDA
input signal
Noise Canceller Block Diagram
f1 (sampling clock)
f1 period
D
Latch
C
Q
D
Latch
C
Q
detection
Match
circuit
Internal SCL
or SDA signal
25. I
2
C bus Interface

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