R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 463

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 434 of 573
Figure 26.4
Timer RA
Timer RA
Hardware LIN Read the Synch Break detection flag
Timer RA
Timer RA
UART0 Communication via UART0
UART0 Communication via UART0
TE bit in U0C1 register ← 1
U0TB register ← 0055h
U0TB register ← ID field
Header Field Transmission Flowchart Example (2)
Read the count status flag
Set the timer to stop counting
Read the count status flag
Set the timer to start counting
TSTART bit in TRACR register ← 1
TCSTF flag in TRACR register
TSTART bit in TRACR register ← 0
TCSTF flag in TRACR register
SBDCT flag in LINST register
SBDCT = 1?
TCSTF = 1?
TCSTF = 0?
YES
YES
YES
A
NO
NO
NO
A Synch Break for timer RA is
generated.
After writing 1 to the TSTART bit,
if registers TRAPRE and TRA for
timer RA are not read or the register
settings are not changed, reading 1
from the TCSTF flag can be omitted.
Zero or one cycle of the timer RA
count source is required after timer
RA starts counting before the TCSTF
flag is set to 1.
A timer RA interrupt can be used to
end Synch Break generation.
One or two cycles of the CPU clock
are required after Synch Break
generation ends before the SBDCT
flag is set to 1.
After a Synch Break for timer RA is
generated, stop the timer count.
After writing 0 to the TSTART bit,
if registers TRAPRE and TRA for
timer RA are not read or the register
settings are not changed, reading 0
from the TCSTF flag can be omitted.
Zero or one cycle of the timer RA
count source is required after timer
RA stops counting before the TCSTF
flag is set to 0.
The Synch Field is transmitted.
The ID field is transmitted.
26. Hardware LIN