R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 468

MCU 1KB FLASH 16K ROM 20-LSSOP

R5F21324CNSP#U0

Manufacturer Part Number
R5F21324CNSP#U0
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Cr
Datasheet

Specifications of R5F21324CNSP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 439 of 573
Figure 26.9
26.4.3
LINCR register
TRAIC register
LINST register
BCDCT flag in
Transfer clock
U0C1 register
The bus collision detection function can be used if UART0 is enabled for transmission (TE bit in U0C1 register
= 1). To detect a bus collision during Synch Break transmission, set the BCE bit in the LINCR2 register to 1
(bus collision detection enabled).
Figure 26.9 shows an Operating Example When Bus Collision is Detected.
LINE bit in
RXD0 pin
TXD0 pin
TE bit in
IR bit in
Bus Collision Detection Function
Operating Example When Bus Collision is Detected
Set to 1 by a program.
Set to 1 by a program.
Set to 0 when an interrupt request is acknowledged
or by a program.
1 is written to B2CLR bit in LINST register.
26. Hardware LIN

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