R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 481

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 452 of 573
Table 27.3
Start process time
A/D conversion
execution time
Between-execution process time
End process time
Table 27.3 shows the Number of Cycles for A/D Conversion Items. The A/D conversion time is defined as
follows.
The start process time varies depending on which φAD is selected.
When 1 (A/D conversion starts) is written to the ADST bit in the ADCON0 register, an A/D conversion starts
after the start process time has elapsed. Reading the ADST bit before the A/D conversion returns 0 (A/D
conversion stops).
In the modes where an A/D conversion is performed on multiple pins or multiple times, the between-execution
process time is inserted between the A/D conversion execution time for one pin and the next A/D conversion
time.
In one-shot mode and single sweep mode, the ADST bit is set to 0 during the end process time and the last A/D
conversion result is stored in the ADi register.
•
•
In on-shot mode
Start process time + A/D conversion execution time + end process time
When two pins are selected in single sweep mode
Start process time + (A/D conversion execution time + between-execution process time + A/D conversion
execution time) + end process time
Number of Cycles for A/D Conversion Items
A/D Conversion Item
φ AD = fAD
φ AD = fAD divided by 2
φ AD = fAD divided by 4
φ AD = fAD divided by 8
Open-circuit detection disabled
Open-circuit detection enabled
1 or 2 fAD cycles
2 or 3 fAD cycles
3 or 4 fAD cycles
5 or 6 fAD cycles
2 or 3 fAD cycles
40 φ AD cycles
42 φ AD cycles
1 φ AD cycle
Number of Cycles
27. A/D Converter