R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 63

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 34 of 573
5.4
Figure 5.7
A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet0. To use voltage monitor 0 reset, set the LVDAS bit in the
OFS register to 0 (voltage monitor 0 reset enabled after reset). The Vdet0 voltage detection level can be changed by
the settings of bits VDSEL0 to VDSEL1 in the OFS register.
When the input voltage to the VCC pin reaches the Vdet0 level or below, the pins, CPU, and SFR are reset.
When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock
start counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock with no
division is automatically selected as the CPU clock after reset.
To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to
0.
Bits VDSEL0 to VDSEL1 and LVDAS cannot be changed by a program. To set these bits, write values to b4 to b6
of address 0FFFFh using a flash programmer.
Refer to 5.1.3 Option Function Select Register (OFS) for details of the OFS register.
Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 0 reset.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet0 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 0 reset.
Figure 5.7 shows an Example of Voltage Monitor 0 Reset Circuit and Operation.
Notes:
Voltage Monitor 0 Reset
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage
2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in
Detection Circuit for details.
the OFS register to 0.
Example of Voltage Monitor 0 Reset Circuit and Operation
Internal reset signal
Power V
External
V
0.5V
det0
CC
circuit response time
Voltage detection 0
f
OCO-S
1
× 32
5. Resets