MC908LJ24CPBER Freescale Semiconductor, MC908LJ24CPBER Datasheet - Page 168

• Manufacturer Part Number: MC908LJ24CPBER
• Description: IC MCU 24K FLASH 4/8MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CPBER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 40
• Ram Memory Size: 768Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Notes:
V
V
1. PTA0 = 1 if serial communication; PTA0 = 0 if parallel communication
2. External clock is derived by a 32.768 kHz crystal or a 4.9152/9.8304 MHz off-chip oscillator
3. Monitor mode entry by IRQ = V
GND
GND
IRQ
TST
TST
V
V
GND
V
or
X
or
DD
DD
DD
(3)
(3)
GND
V
V
V
V
RST
V
V
V
V
V
or
TST
or
TST
TST
or
TST
DD
DD
DD
DD
DD
Not Blank
Address
"$FFFF"
"$FFFF"
"$FFFF"
$FFFE/
$FFFF
Blank
Blank
Blank
X
X
X
Table 10-1. Monitor Mode Signal Requirements and Options
PTA2
X
X
X
X
X
0
0
TST
, a 4.9152/9.8304 MHz off-chip oscillator must be used. The MCU internal crystal oscillator circuit is bypassed.
PTA1
X
1
1
X
X
X
X
PTA0
X
1
1
1
1
X
X
(1)
PTC1
X
0
1
X
X
X
X
External
Clock
4.9152
9.8304
9.8304
32.768
MHz
MHz
MHz
kHz
X
X
X
(2)
Frequency
2.4576
2.4576
2.4576
2.4576
MHz
MHz
MHz
MHz
Bus
—
—
0
OFF
OFF
OFF
OFF
OFF
PLL
ON
X
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
COP
Baud
Rate
9600
9600
9600
9600
—
—
0
No operation until
reset goes high
PTA1 and PTA2
voltages only
required if
IRQ = V
PTC1 determines
frequency divider
PTA1 and PTA2
voltages only
required if
IRQ = V
PTC1 determines
frequency divider
External frequency
always divided by 4
PLL enabled
(BCS set)
in monitor code
Enters user
mode — will
encounter an illegal
address reset
Enters user mode
Comment
TST
TST
;
;