MC908LJ24CPBER Freescale Semiconductor, MC908LJ24CPBER Datasheet - Page 304

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MC908LJ24CPBER

Manufacturer Part Number
MC908LJ24CPBER
Description
IC MCU 24K FLASH 4/8MHZ 64-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ24CPBER

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
HC08
No. Of I/o's
40
Ram Memory Size
768Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908LJ24CPBER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Serial Peripheral Interface Module (SPI)
14.9 Interrupts
Data Sheet
304
NOTE:
slave. This happens because SS at logic 0 indicates the start of the
transmission (MISO driven out with the value of MSB) for CPHA = 0.
When CPHA = 1, a slave can be selected and then later unselected with
no transmission occurring. Therefore, MODF does not occur since a
transmission was never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI
receiver/error CPU interrupt request if the ERRIE bit is set. The MODF
bit does not clear the SPE bit or reset the SPI in any way. Software can
abort the SPI transmission by clearing the SPE bit of the slave.
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK
clocks, even if it was already in the middle of a transmission.
To clear the MODF flag, read the SPSCR with the MODF bit set and then
write to the SPCR register. This entire clearing mechanism must occur
with no MODF condition existing or else the flag is not cleared.
Four SPI status flags can be enabled to generate CPU interrupt
requests.
SPTE
Transmitter empty
SPRF
Receiver full
OVRF
Overflow
MODF
Mode fault
Serial Peripheral Interface Module (SPI)
Flag
Table 14-2. SPI Interrupts
SPI transmitter CPU interrupt request
(DMAS = 0, SPTIE = 1, SPE = 1)
SPI receiver CPU interrupt request
(DMAS = 0, SPRIE = 1)
SPI receiver/error interrupt request (ERRIE = 1)
SPI receiver/error interrupt request (ERRIE = 1)
MC68HC908LJ24/LK24 — Rev. 2.1
Request
Freescale Semiconductor

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