MC908LJ24CPBER Freescale Semiconductor, MC908LJ24CPBER Datasheet - Page 338

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MC908LJ24CPBER

Manufacturer Part Number
MC908LJ24CPBER
Description
IC MCU 24K FLASH 4/8MHZ 64-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ24CPBER

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
HC08
No. Of I/o's
40
Ram Memory Size
768Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908LJ24CPBER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Analog-to-Digital Converter (ADC)
16.4.4 Continuous Conversion
16.4.5 Result Justification
Data Sheet
338
In the continuous conversion mode, the ADC continuously converts the
selected channel, filling the ADC data register (ADRH:ADRL) with new
data after each conversion. Data from the previous conversion will be
overwritten whether that data has been read or not. Conversions will
continue until the ADCO bit is cleared. The COCO bit is set after each
conversion and can be cleared by writing to the ADC status and control
register or reading of the ADRL data register.
The conversion result may be formatted in four different ways.
All four of these modes are controlled using MODE0 and MODE1 bits
located in the ADC clock control register (ADCLK).
Left justification will place the eight most significant bits (MSB) in the
ADC data register high (ADRH). This may be useful if the result is to be
treated as an 8-bit result where the least significant two bits, located in
the ADC data register low (ADRL) can be ignored. However, ADRL must
be read after ADRH or else the interlocking will prevent all new
conversions from being stored.
Right justification will place only the two MSBs in the corresponding ADC
data register high (ADRH) and the eight LSB bits in ADC data register
low (ADRL). This mode of operation typically is used when a 10-bit
unsigned result is desired.
Left justified sign data mode is similar to left justified mode with one
exception. The MSB of the 10-bit result, AD9 located in ADRH is
complemented. This mode of operation is useful when a result,
represented as a signed magnitude from mid-scale, is needed.
Left justified
Right justified
Left justified sign data mode
8-bit truncation
Analog-to-Digital Converter (ADC)
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor

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