MC908LJ24CPBER Freescale Semiconductor, MC908LJ24CPBER Datasheet - Page 344

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MC908LJ24CPBER

Manufacturer Part Number
MC908LJ24CPBER
Description
IC MCU 24K FLASH 4/8MHZ 64-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ24CPBER

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
HC08
No. Of I/o's
40
Ram Memory Size
768Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908LJ24CPBER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Analog-to-Digital Converter (ADC)
16.8.2 ADC Data Register
Data Sheet
344
Addr.
$003D
Addr.
$003D
$003E
$003E
ADC Data Register High
ADC Data Register High
ADC Data Register Low
ADC Data Register Low
Register Name
Register Name
Figure 16-5. ADRH and ADRL in 8-Bit Truncated Mode
(ADRH)
(ADRH)
(ADRL)
(ADRL)
Figure 16-6. ADRH and ADRL in Right Justified Mode
The ADC data register consist of a pair of 8-bit registers: high byte
(ADRH), and low byte (ADRL). This pair form a 16-bit register to store
the 10-bit ADC result for the selected ADC result justification mode.
In 8-bit truncated mode, the ADRL holds the eight most significant bits
(MSBs) of the 10-bit result. The ADRL is updated each time an ADC
conversion completes. In 8-bit truncated mode, ADRL contains no
interlocking with ADRH. (See
Truncated
In right justified mode the ADRH holds the two MSBs, and the ADRL
holds the eight least significant bits (LSBs), of the 10-bit result. ADRH
and ADRL are updated each time a single channel ADC conversion
completes. Reading ADRH latches the contents of ADRL. Until ADRL is
read all subsequent ADC results will be lost.
(See
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Figure 16-6 . ADRH and ADRL in Right Justified
Bit 7
Bit 7
AD9
AD7
Analog-to-Digital Converter (ADC)
R
R
R
R
0
0
0
0
0
0
Mode.)
AD8
AD6
R
R
R
R
6
0
0
0
6
0
0
0
AD7
AD5
R
R
R
R
5
0
0
0
5
0
0
0
Figure 16-5 . ADRH and ADRL in 8-Bit
AD6
AD4
R
R
R
R
4
0
0
0
4
0
0
0
AD5
AD3
MC68HC908LJ24/LK24 — Rev. 2.1
R
R
R
R
3
0
0
0
3
0
0
0
AD4
AD2
Freescale Semiconductor
R
R
R
R
0
0
0
0
0
0
2
2
Mode.)
AD3
AD9
AD1
R
R
R
R
1
0
0
0
1
0
0
Bit 0
Bit 0
AD2
AD8
AD0
R
R
R
R
0
0
0
0
0

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