MC908LJ24CFUER Freescale Semiconductor, MC908LJ24CFUER Datasheet - Page 147

IC MCU 24K FLASH 8MHZ SPI 64-QFP

MC908LJ24CFUER

Manufacturer Part Number
MC908LJ24CFUER
Description
IC MCU 24K FLASH 8MHZ SPI 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ24CFUER

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908LJ24CFUER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
9.4.2.2 Computer Operating Properly (COP) Reset
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
CGMOUT
PORRST
OSC1
IRST
ICLK
RST
IAB
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and bits 12 through 5
of the SIM counter. The SIM counter output, which occurs at least every
2
serviced as soon as possible out of reset to guarantee the maximum
amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ pin is held at V
while the MCU is in monitor mode. The COP module can be disabled
only through combinational logic conditioned with the high voltage signal
on the RST or the IRQ pin. This prevents the COP from becoming
disabled as a result of external noise. During a break state, V
RST pin disables the COP module.
13
CYCLES
4096
– 2
4
ICLK cycles, drives the COP counter. The COP should be
Figure 9-7. POR Recovery
System Integration Module (SIM)
CYCLES
32
CYCLES
32
System Integration Module (SIM)
$FFFE
Reset and System Initialization
$FFFF
TST
Data Sheet
on the
TST
147

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