MC908LJ24CFUER Freescale Semiconductor, MC908LJ24CFUER Datasheet - Page 381

• Manufacturer Part Number: MC908LJ24CFUER
• Description: IC MCU 24K FLASH 8MHZ SPI 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CFUER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.3.2 Data Direction Register A (DDRA)
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
NOTE:
NOTE:
Address:
ADC[3:0] — ADC channels 0 to 3
Care must be taken when reading port A while applying analog voltages
to ADC[3:0] pins. If the appropriate ADC channel is not enabled,
excessive current drain may occur if analog voltages are applied to the
PTAx/ADCx pin, while PTA is read as a digital input. Those ports not
selected as analog input channels are considered digital I/O ports.
Data direction register A determines whether each port A pin is an input
or an output. Writing a logic 1 to a DDRA bit enables the output buffer for
the corresponding port A pin; a logic 0 disables the output buffer.
DDRA[7:0] — Data Direction Register A Bits
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
the port A I/O logic.
Reset:
Read:
Write:
ADC[3:0] are pins used for the input channels to the analog-to-digital
converter module. The channel select bits, ADCH[4:0], in the ADC
status and control register define which port pin will be used as an
ADC input and overrides any control from the port I/O logic. See
Section 16. Analog-to-Digital Converter
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
DDRA7
$0004
Bit 7
0
Figure 18-3. Data Direction Register A (DDRA)
Input/Output (I/O) Ports
DDRA6
6
0
DDRA5
5
0
DDRA4
4
0
DDRA3
3
0
(ADC).
DDRA2
2
0
Figure 18-4
Input/Output (I/O) Ports
DDRA1
1
0
Data Sheet
shows
DDRA0
Bit 0
Port A
0
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