MC908LJ24CFUER Freescale Semiconductor, MC908LJ24CFUER Datasheet - Page 418

• Manufacturer Part Number: MC908LJ24CFUER
• Description: IC MCU 24K FLASH 8MHZ SPI 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CFUER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Computer Operating Properly (COP)
21.4.5 Internal Reset
21.4.6 Reset Vector Fetch
21.4.7 COPD (COP Disable)
21.4.8 COPRS (COP Rate Select)
Data Sheet
418
†† Reset by POR only.
Address:
An internal reset clears the COP prescaler and the COP counter.
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the COP prescaler.
The COPD signal reflects the state of the COP disable bit (COPD) in the
CONFIG1 register. (See
Registers
The COPRS signal reflects the state of the COP rate select bit (COPRS)
in the CONFIG1 register.
COPRS — COP Rate Select
COPD — COP Disable Bit
Reset:
Read:
Write:
COPRS selects the COP time-out period. Reset clears COPRS.
COPD disables the COP module.
1 = COP time out period = 2
0 = COP time out period = 2
1 = COP module disabled
0 = COP module enabled
COPRS
$001F
Computer Operating Properly (COP)
Bit 7
Figure 21-2. Configuration Register 1 (CONFIG1)
0
(CONFIG).)
LVISTOP LVIRSTD LVIPWRD
6
0
Figure 21-2
5
0
= Unimplemented
0
13
18
4
††
– 2
– 2
and
4
4
ICLK cycles
ICLK cycles
MC68HC908LJ24/LK24 — Rev. 2.1
Section 5. Configuration
3
0
0
SSREC
Freescale Semiconductor
2
0
STOP
1
0
COPD
Bit 0
0