R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 213
R5F21324ANSP#U1
Manufacturer Part Number
R5F21324ANSP#U1
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Ar
Datasheet
1.R5F21322ANSPU1.pdf
(629 pages)
Specifications of R5F21324ANSP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 183 of 583
15.3.10 DTC Activation Source Acknowledgement and Interrupt Source Flags
15.3.10.1 Interrupt Sources Except for Flash Memory, Timer RC, and Synchronous
15.3.10.2 Flash Memory
15.3.10.3 Timer RC
When the DTC activation source is an interrupt source except for the flash memory, timer RC, or the
synchronous serial communication unit/I
to 12 cycles of the CPU clock after the interrupt source is generated. If an interrupt source is generated when a
software command is executed, the same DTC activation source cannot be acknowledged for 9 to 16 cycles of
the CPU clock. If a DTC activation source is generated during DTC operation and acknowledged, the same
DTC activation source cannot be acknowledged for 8 to 12 cycles of the CPU clock on completion of the DTC
transfer immediately before the DTC is activated by the source. When a software command is executed on
completion of the DTC transfer immediately before the DTC is activated, the same DTC activation source
cannot be acknowledged for 16 cycles of the CPU clock.
When the DTC activation source is flash ready status, even if a flash ready status interrupt request is generated,
it is not acknowledged as the DTC activation source after the RDYSTI bit in the FST register is set to 1 (flash
ready status interrupt request) and before the DTC sets the RDYSTI bit to 0 (no flash ready status interrupt
request). If a flash ready status interrupt request is generated after the DTC sets the RDYSTI bit to 0, the DTC
acknowledges it as the activation source. 8 to 12 cycles of the CPU clock are required after the RDYSTI bit is
set to 1 and before the DTC sets the interrupt request flag to 0. If a flash ready status interrupt is generated when
a software command is executed, 9 to 16 cycles of the CPU clock are required before the DTC sets the interrupt
source flag to 0. If a flash ready status interrupt request is generated during DTC operation and acknowledged
as the DTC activation source, the RDYSTI bit is set to 0 after 8 to 12 cycles of the CPU clock on completion of
the DTC transfer immediately before the DTC is activated by the source. When a software command is
executed on completion of the DTC transfer immediately before the DTC is activated, the RDYSTI bit is set to
0 after 16 cycles of the CPU clock.
When the DTC activation source is an interrupt source for timer RC, even if an input capture/compare match in
individual timers occurs, it is not acknowledged as the DTC activation source after the interrupt source flag is
set to 1 and before the DTC sets the flag to 0. If an input capture/compare match occurs after the DTC sets the
interrupt source flag to 0, the DTC acknowledges it as the activation source. 8 to 12 cycles of the CPU clock
plus 0.5 to 1.5 cycles of the timer operating clock are required after the interrupt source flag is set to 1 and
before the DTC sets the flag to 0. If the interrupt request flag is set to 1 when a software command is executed,
9 to 16 cycles of the CPU clock plus 0.5 to 1.5 cycles of the timer operating clock are required before the DTC
sets the interrupt source flag to 0. If individual DTC activation sources are generated for timer RC during DTC
operation and acknowledged, the interrupt source flag is set to 0 after 8 to 12 cycles of the CPU clock plus 0.5
to 1.5 cycles of the timer operating clock on completion of the DTC transfer immediately before the DTC is
activated by the source. When a software command is executed on completion of the DTC transfer immediately
before the DTC is activated, the interrupt source flag is set to 0 after 16 cycles of the CPU clock plus 0.5 to 1.5
cycles of the timer operating clock.
Serial Communication Unit (SSU)/I
Preliminary specification
Specifications in this manual are tentative and subject to change.
Nov 05, 2008
2
C bus, the same DTC activation source cannot be acknowledged for 8
2
C bus
15. DTC
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