R5F21334CNFP#U0 Renesas Electronics America, R5F21334CNFP#U0 Datasheet - Page 411

• Manufacturer Part Number: R5F21334CNFP#U0
• Description: MCU 1KB FLASH 16K ROM 32-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/33Cr

Specifications of R5F21334CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/33C Group
REJ09B0570-0100 Rev.1.00 Dec. 14, 2009
Page 381 of 589
24.2.10 SS Status Register (SSSR)
Notes:
After Reset
1. Writing 1 to CE, ORER, RDRF, TEND, or TDRE bits is invalid. To set any of these bits to 0, first read 1 then write
2. When the serial communication is started while the SSUMS bit in the SSMR2 register is set to 1 (four-wire bus
3. Indicates when overrun errors occur and receive completes by error reception. If the next serial data receive
4. The RDRF bit is set to 0 when reading out the data from the SSRDR register.
5. Bits TEND and TDRE are set to 0 when writing data to the SSTDR register.
6. The TDRE bit is set to 1 when the TE bit in the SSER register is set to 1 (transmit enabled).
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 019Ch
0.
communication mode) and the MSS bit in the SSCRH register is set to 1 (operates as master device), the CE bit
is set to 1 if “L” is applied to the SCS pin input. Refer to 24.5.4 SCS Pin Control and Arbitration for more
information.
When the SSUMS bit in the SSMR2 register is set to 1 (four-wire bus communication mode), the MSS bit in the
SSCRH register is set to 0 (operates as slave device) and the SCS pin input changes the level from “L” to “H”
during transfer, the CE bit is set to 1.
operation is completed while the RDRF bit is set to 1 (data in the SSRDR register), the ORER bit is set to 1.
After the ORER bit is set to 1 (overrun error), receive operation is disabled while the bit remains 1.
If the SSSR register is accessed continuously, insert one or more NOP instructions between the instructions
used for access.
Symbol
Symbol
ORER
Bit
RDRF
TEND
TDRE
CE
—
—
—
TDRE
b7
0
Conflict error flag
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Overrun error flag
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Receive data register full flag
Transmit end flag
Transmit data empty flag
TEND
b6
0
Bit Name
(1)
RDRF
(1, 5)
(1)
b5
0
(1, 5, 6)
(1, 4)
b4
—
0
0: No conflict errors generated
1: Conflict errors generated
0: No overrun errors generated
1: Overrun errors generated
0: No data in SSRDR register
1: Data in SSRDR register
0: The TDRE bit is set to 0 when transmitting the last
1: The TDRE bit is set to 1 when transmitting the last
0: Data is not transferred from registers SSTDR to
1: Data is transferred from registers SSTDR to
bit of transmit data
bit of transmit data
SSTRSR
SSTRSR
b3
—
0
24. Synchronous Serial Communication Unit (SSU)
ORER
b2
0
Function
b1
—
0
(2)
(3)
CE
b0
0
R/W
R/W
R/W
R/W
R/W
R/W
—
—