R5F21334CNFP#U0 Renesas Electronics America, R5F21334CNFP#U0 Datasheet - Page 440

MCU 1KB FLASH 16K ROM 32-LQFP

R5F21334CNFP#U0

Manufacturer Part Number
R5F21334CNFP#U0
Description
MCU 1KB FLASH 16K ROM 32-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/3x/33Cr
Datasheet

Specifications of R5F21334CNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
27
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R8C/33C Group
REJ09B0570-0100 Rev.1.00 Dec. 14, 2009
Page 410 of 589
25.2.6
Notes:
After Reset
1. Set according to the necessary transfer rate in master mode. Refer to Tables 25.4 and 25.5 Transfer Rate
2. Rewrite the TRS bit between transfer frames.
3. When the first 7 bits after the start condition in slave receive mode match the slave address set in the SAR
4. In master mode with the I
5. When an overrun error occurs in master receive mode with the clock synchronous serial format, the MST bit is
6. In multimaster operation, use the MOV instruction to set bits TRS and MST.
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0198h
Examples for the transfer rate. This bit is used for maintaining the setup time in transmit mode of slave mode.
The time is 10Tcyc when the CKS3 bit is set to 0 and 20Tcyc when the CKS3 bit is set to 1. (1Tcyc = 1/f1(s))
register and the 8th bit is set to 1, the TRS bit is set to 1.
slave receive mode.
set to 0 and the I
Symbol
Symbol
RCVD
Bit
CKS0
CKS1
CKS2
CKS3
MST
TRS
ICE
IIC bus Control Register 1 (ICCR1)
ICE
b7
0
Transmit clock select bits 3 to 0
Transfer/receive select bit
Master/slave select bit
Receive disable bit
I
2
C bus interface enable bit
2
C bus enters slave receive mode.
RCVD
b6
0
2
Bit Name
C bus format, if arbitration is lost, bits MST and TRS are set to 0 and the IIC enters
MST
b5
0
(5, 6)
(2, 3, 6)
TRS
b4
0
(1)
b3 b2 b1 b0
b5 b4
After reading the ICDRR register while the TRS bit is
set to 0
0: Next receive operation continues
1: Next receive operation disabled
0: This module is halted
1: This module is enabled for transfer operations
0 0 0 0: f1/28
0 0 0 1: f1/40
0 0 1 0: f1/48
0 0 1 1: f1/64
0 1 0 0: f1/80
0 1 0 1: f1/100
0 1 1 0: f1/112
0 1 1 1: f1/128
1 0 0 0: f1/56
1 0 0 1: f1/80
1 0 1 0: f1/96
1 0 1 1: f1/128
1 1 0 0: f1/160
1 1 0 1: f1/200
1 1 1 0: f1/224
1 1 1 1: f1/256
0 0: Slave Receive Mode
0 1: Slave Transmit Mode
1 0: Master Receive Mode
1 1: Master Transmit Mode
(Pins SCL and SDA are set to a port function)
(Pins SCL and SDA are in a bus drive state)
CKS3
b3
0
CKS2
b2
0
Function
CKS1
(4)
b1
0
CKS0
b0
0
25. I
2
C bus Interface
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

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