R5F21334CNFP#U0 Renesas Electronics America, R5F21334CNFP#U0 Datasheet - Page 527

• Manufacturer Part Number: R5F21334CNFP#U0
• Description: MCU 1KB FLASH 16K ROM 32-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/33Cr

Specifications of R5F21334CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/33C Group
REJ09B0570-0100 Rev.1.00 Dec. 14, 2009
Page 497 of 589
30.4.2
Notes:
After Reset
1. To set this bit to 1, first write 0 and then 1 immediately. Disable interrupts and DTC activation between writing 0
2. Write to the FMSTP bit by a program transferred to the RAM. The FMSTP bit is enabled when the FMR01 bit is
3. The CMDRST bit is enabled when the FMR01 bit is set to 1 (CPU rewrite mode enabled) and the FST7 bit in the
4. To set the FMR01 bit to 0 (CPU rewrite mode disabled), set it when the RDYSTI bit in the FST register is set to 0
FMR01 Bit (CPU Rewrite Mode Select Bit)
FMR02 Bit (EW1 Mode Select Bit)
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 01B4h
and writing 1.
set to 1 (CPU rewrite mode enabled). To set the FMSTP bit to 1 (flash memory stops), set it when the FST7 bit in
the FST register is set to 1 (ready).
FST register is set to 0 (busy).
(no flash ready status interrupt request) and the BSYAEI bit is set to 0 (no flash access error interrupt request).
When the FMR01 bit is set to 1 (CPU rewrite mode enabled), the MCU is made ready to accept software
commands.
When the FMR02 bit is set to 1 (EW1 mode), EW1 mode is selected.
Symbol RDYSTIE BSYAEIE CMDERIE CMDRST FMSTP
CMDERIE Erase/write error interrupt enable bit
RDYSTIE Flash ready status interrupt enable bit 0: Flash ready status interrupt disabled
CMDRST Erase/write sequence reset bit
BSYAEIE Flash access error interrupt enable bit 0: Flash access error interrupt disabled
Bit
Symbol
FMSTP
FMR01
FMR02
Flash Memory Control Register 0 (FMR0)
—
b7
0
Reserved bit
CPU rewrite mode select bit
EW1 mode select bit
Flash memory stop bit
b6
0
Bit Name
b5
0
(1)
(2)
(1, 4)
b4
(3)
0
Set to 0.
0: CPU rewrite mode disabled
1: CPU rewrite mode enabled
0: EW0 mode
1: EW1 mode
0: Flash memory operates
1: Flash memory stops
When the CMDRST bit is set to 1, the erase/write
sequence is reset and erasure/writing can be
forcibly stopped.
When read, the content is 0.
0: Erase/write error interrupt disabled
1: Erase/write error interrupt enabled
1: Flash access error interrupt enabled
1: Flash ready status interrupt enabled
(Low-power consumption state, flash memory
b3
initialization)
0
FMR02
b2
0
Function
FMR01
b1
0
b0
—
0
30. Flash Memory
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W