MC908LJ24CFQE Freescale Semiconductor, MC908LJ24CFQE Datasheet - Page 275

• Manufacturer Part Number: MC908LJ24CFQE
• Description: IC MCU 24K FLASH 8MHZ SPI 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CFQE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 48
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Controller Family/series: HC08
• No. Of I/o's: 48
• Ram Memory Size: 768Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
CAUTION:
CAUTION:
Infrared Serial Communications Interface Module (IRSCI)
DMARE — DMA Receive Enable Bit
The DMA module is not included on this MCU. Writing a logic 1 to
DMARE or DMATE may adversely affect MCU performance.
DMATE — DMA Transfer Enable Bit
The DMA module is not included on this MCU. Writing a logic 1 to
DMARE or DMATE may adversely affect MCU performance.
ORIE — Receiver Overrun Interrupt Enable Bit
NEIE — Receiver Noise Error Interrupt Enable Bit
FEIE — Receiver Framing Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the receiver overrun bit, OR. Reset clears ORIE.
This read/write bit enables SCI error CPU interrupt requests
generated by the noise error bit, NE. Reset clears NEIE.
This read/write bit enables SCI error CPU interrupt requests
generated by the framing error bit, FE. Reset clears FEIE.
1 = DMA not enabled to service SCI receiver DMA service requests
0 = DMA not enabled to service SCI receiver DMA service requests
1 = SCTE DMA service requests enabled; SCTE CPU interrupt
0 = SCTE DMA service requests disabled; SCTE CPU interrupt
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
generated by the SCRF bit (SCI receiver CPU interrupt
requests enabled)
generated by the SCRF bit (SCI receiver CPU interrupt
requests enabled)
requests disabled
requests enabled
Infrared Serial Communications Interface Module (IRSCI)
I/O Registers
Data Sheet
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