R5F21272SNFP#U0 Renesas Electronics America, R5F21272SNFP#U0 Datasheet - Page 163

IC R8C/27 MCU FLASH 32LQFP

R5F21272SNFP#U0

Manufacturer Part Number
R5F21272SNFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21272SNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 14.2
Timer RA Control Register
Timer RA I/O Control Register
b7 b6 b5 b4
NOTES:
b7 b6 b5 b4
1.
2.
3.
4.
5.
Refer to 14.1.6 Notes on Tim er RA for precautions regarding bits TSTART and TCSTF.
When the TSTOP bit is set to 1, bits TSTART and TCSTF and registers TRAPRE and TRA are set to the values after a
reset.
Bits TEDGF and TUNDF can be set to 0 by w riting 0 to these bits by a program. How ever, their value remains
unchanged w hen 1 is w ritten.
In pulse w idth measurement mode and pulse period measurement mode, use the MOV instruction to set the TRACR
register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, w rite 1 to them.
Set to 0 in timer mode, pulse output mode, and event counter mode.
Sep 26, 2008
b3 b2
b3 b2
Registers TRACR and TRAIOC
b1 b0
b1 b0
Bit Symbol
Bit Symbol
TEDGSEL
TSTART
(b7-b6)
TRAIOC
Symbol
TRACR
TSTOP
TEDGF
TUNDF
TOENA
TIOSEL
(b7-b6)
TCSTF
Symbol
TOPCR
TIPF0
TIPF1
(b3)
Page 144 of 453
(4)
Timer RA count start bit
Timer RA count status flag
Timer RA count forcible stop
bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Active edge judgment
flag
Timer RA underflow flag
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAIO polarity sw itch bit
TRAIO output control bit
TRAO output enable bit
_____
INT1
TRAIO input filter select bits
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
(2)
(3, 5)
/TRAIO select bit
Address
Bit Name
Address
Bit Name
0100h
0101h
(1)
(3, 5)
(1)
0 : Count stops
1 : Count starts
0 : Count stops
1 : During count
When this bit is set to 1, the count is forcibly
stopped. When read, its content is 0.
0 : Active edge not received
1 : Active edge received
0 : No underflow
1 : Underflow
Function varies depending on operating mode.
(end of measurement period)
After Reset
After Reset
Function
Function
00h
00h
14. Timers
RW
RW
RW
RW
RW
RO
RW
RW
RW
RW
RW
RW

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