R5F21272SNFP#U0 Renesas Electronics America, R5F21272SNFP#U0 Datasheet - Page 254

• Manufacturer Part Number: R5F21272SNFP#U0
• Description: IC R8C/27 MCU FLASH 32LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/27r

Specifications of R5F21272SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 14.74
Figure 14.75
Timer RE Control Register 1
Timer RE Control Register 2
b7 b6 b5 b4 b3 b2
b7 b6 b5 b4 b3 b2
0 0
Sep 26, 2008
0
0
0 0
TRECR1 Register in Output Compare Mode
TRECR2 Register in Output Compare Mode
b1 b0
b1 b0
0 0
Bit Symbol
Bit Symbol
H12_H24
TSTART
TRECR1
TRERST
TRECR2
TOENA
(b7-b6)
Symbol
Symbol
TCSTF
COMIE
DYIE
WKIE
SEIE
MNIE
HRIE
(b0)
INT
PM
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Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RE count status flag
TREO pin output enable bit
Interrupt request timing bit
Timer RE reset bit
A.m./p.m. bit
Operating mode select bit
Timer RE count start bit
Periodic interrupt triggered every
second enable bit
Periodic interrupt triggered every
minute enable bit
Periodic interrupt triggered every
hour enable bit
Periodic interrupt triggered every
day enable bit
Periodic interrupt triggered every
w eek enable bit
Compare match interrupt enable bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Address
Bit Name
011Ch
Address
Bit Name
011Dh
0 : Count stopped
1 : Counting
0 : Disable clock output
1 : Enable clock output
Set to 0 in output compare mode.
When setting this bit to 0, after setting it to 1, the
follow ing w ill occur.
• Registers TRESEC, TREMIN, TREHR, TREWK,
• Bits TCSTF, INT, PM, H12_H24, and
• The 8-bit counter is set to 00h and
Set to 0 in output compare mode.
0 : Count stops
1 : Count starts
and TRECR2 are set to 00h.
TSTART in the TRECR1 register are
set to 0.
the 4-bit counter is set to 0h.
Set to 0 in output compare mode.
0 : Disable compare match interrupt
1 : Enable compare match interrupt
After Reset
Function
After Reset
00h
Function
00h
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
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