R5F21272SNFP#U0 Renesas Electronics America, R5F21272SNFP#U0 Datasheet - Page 267

IC R8C/27 MCU FLASH 32LQFP

R5F21272SNFP#U0

Manufacturer Part Number
R5F21272SNFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21272SNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
15.1
Table 15.1
i = 0 or 1
NOTES:
Transfer data format
Transfer clocks
Transmit start conditions
Receive start conditions
Interrupt request
generation timing
Error detection
Select functions
In the clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.
Table 15.1 lists the Specifications of Clock Synchronous Serial I/O Mode. Table 15.2 lists the Registers Used and
Settings in Clock Synchronous Serial I/O Mode.
1. If an external clock is selected, ensure that the external clock is “H” when the CKPOL bit in the
2. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR
U0C0 register is set to 0 (transmit data output at falling edge and receive data input at rising edge of
transfer clock), and that the external clock is “L” when the CKPOL bit is set to 1 (transmit data output
at rising edge and receive data input at falling edge of transfer clock).
bit in the SiRIC register remains unchanged.
Clock Synchronous Serial I/O Mode
Sep 26, 2008
Item
Specifications of Clock Synchronous Serial I/O Mode
Page 248 of 453
• Transfer data length: 8 bits
• CKDIR bit in UiMR register is set to 0 (internal clock): fi/(2(n+1))
• The CKDIR bit is set to 1 (external clock): input from CLKi pin
• Before transmit starts, the following requirements must be met
• Before receive starts, the following requirements must be met
• When transmitting, one of the following conditions can be selected
• When receiving
• Overrun error
• CLK polarity selection
• LSB first, MSB first selection
• Continuous receive mode selection
fi = f1, f8, f32 n = value set in U0BRG register: 00h to FFh
- The TE bit in the UiC1 register is set to 1 (transmission enabled)
- The TI bit in the UiC1 register is set to 0 (data in the UiTB register)
- The RE bit in the UiC1 register is set to 1 (reception enabled)
- The TE bit in the UiC1 register is set to 1 (transmission enabled)
- The TI bit in the UiC1 register is set to 0 (data in the UiTB register)
- The UiIRS bit is set to 0 (transmit buffer empty):
- The UiIRS bit is set to 1 (transmission completes):
When data transfer from the UARTi receive register to the UiRB register
(when reception completes).
This error occurs if the serial interface starts receiving the next data item
before reading the UiRB register and receives the 7th bit of the next data.
Transfer data input/output can be selected to occur synchronously with
the rising or the falling edge of the transfer clock.
Whether transmitting or receiving data begins with bit 0 or begins with bit 7
can be selected.
Receive is enabled immediately by reading the UiRB register.
When transferring data from the UiTB register to UARTi transmit register
(when transmission starts).
When completing data transmission from UARTi transmit register.
(2)
Specification
15. Serial Interface
(1)
(1)

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