R5F21272SNFP#U0 Renesas Electronics America, R5F21272SNFP#U0 Datasheet - Page 270

• Manufacturer Part Number: R5F21272SNFP#U0
• Description: IC R8C/27 MCU FLASH 32LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/27r

Specifications of R5F21272SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 15.9
Figure 15.10
15.1.1
15.1.2
transfer clock polarity.
Figure 15.10 shows the Transfer Format. Use the UFORM bit in the UiC0 (i = 0 or 1) register to select the
transfer format.
Figure 15.9 shows the Transfer Clock Polarity. Use the CKPOL bit in the UiC0 (i = 0 or 1) register to select the
Sep 26, 2008
Polarity Select Function
LSB First/MSB First Select Function
Transfer Clock Polarity
Transfer Format
CLKi
CLKi
• When the CKPOL bit in the UiC0 register = 0 (output transmit data at the falling
• When the CKPOL bit in the UiC0 register = 1 (output transmit data at the rising
• When UFORM bit in UiC0 register = 0 (LSB first)
• When UFORM bit in UiC0 register = 1 (MSB first)
RXDi
RXDi
TXDi
TXDi
RXDi
RXDi
CLKi
TXDi
CLKi
TXDi
edge and input receive data at the rising edge of the transfer clock)
edge and input receive data at the falling edge of the transfer clock)
NOTES:
NOTE:
i = 0 or 1
i = 0 or 1
(1)
(2)
1. When not transferring, the CLKi pin level is “H”.
2. When not transferring, the CLKi pin level is “L”.
1. The above applies when the CKPOL bit in the UiC0 register is
data at the rising edge of the transfer clock).
set to 0 (output transmit data at the falling edge and input receive
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D0
D0
D7
D7
D0
D0
D0
D0
D1
D1
D1
D1
D1
D1
D6
D6
D2
D2
D2
D2
D2
D2
D5
D5
D3
D3
D3
D3
D3
D3
D4
D4
(1)
D4
D4
D4
D4
D4
D4
D3
D3
(1)
D5
D5
D5
D5
D5
D5
D2
D2
D6
D6
D6
D6
D6
D6
D1
D1
D7
D7
D7
D7
D7
D7
D0
D0
15. Serial Interface