R5F21272SNFP#U0 Renesas Electronics America, R5F21272SNFP#U0 Datasheet - Page 32
Manufacturer Part Number
IC R8C/27 MCU FLASH 32LQFP
Renesas Electronics America
Specifications of R5F21272SNFP#U0
I²C, LIN, SIO, SSU, UART/USART
LED, POR, Voltage Detect, WDT
Number Of I /o
Program Memory Size
8KB (8K x 8)
Program Memory Type
512 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
-20°C ~ 85°C
Package / Case
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Bonase Electronics (HK) Co., Limited
R8C/26 Group, R8C/27 Group
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 to be used
as a 32-bit address register (A1A0).
FB is a 16-bit register for FB relative addressing.
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
PC is 20 bits wide and indicates the address of the next instruction to be executed.
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
SB is a 16-bit register for SB relative addressing.
FLG is an 11-bit register indicating the CPU state.
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
The D flag is for debugging only. Set it to 0.
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
Data Registers (R0, R1, R2, and R3)
Address Registers (A0 and A1)
Frame Base Register (FB)
Interrupt Table Register (INTB)
Program Counter (PC)
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Static Base Register (SB)
Flag Register (FLG)
Sep 26, 2008
Carry Flag (C)
Debug Flag (D)
Zero Flag (Z)
Sign Flag (S)
Register Bank Select Flag (B)
Overflow Flag (O)
Page 13 of 453
2. Central Processing Unit (CPU)