R5F21272SNFP#U0 Renesas Electronics America, R5F21272SNFP#U0 Datasheet - Page 330

IC R8C/27 MCU FLASH 32LQFP

R5F21272SNFP#U0

Manufacturer Part Number
R5F21272SNFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21272SNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21272SNFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
R5F21272SNFP#U0
Manufacturer:
SAMSUNG
Quantity:
300 000
Company:
Part Number:
R5F21272SNFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
R5F21272SNFP#U0R5F21272SNFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
R5F21272SNFP#U0R5F21272SNFP#X6
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
16.3.3.5
In slave receive mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal.
Figures 16.38 and 16.39 show the Operating Timing in Slave Receive Mode (I
The receive procedure and operation in slave receive mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits WAIT and MLS in the
(2) When the slave address matches at the 1st frame after detecting the start condition, the slave device
(3) Read the ICDRR register every time the RDRF bit is set to 1. If the 8th clock cycle falls while the
(4) Reading the last byte is performed by reading the ICDRR register in like manner.
Sep 26, 2008
ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Set bits TRS and MST in
the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.
outputs the level set in the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock
cycle. Since the RDRF bit in the ICSR register is set to 1 simultaneously, perform the dummy-read (the
read data is unnecessary because it indicates the slave address and R/W).
RDRF bit is set to 1, the SCL signal is fixed “L” until the ICDRR register is read. The setting change of
the acknowledge signal returned to the master device before reading the ICDRR register takes affect
from the following transfer frame.
Slave Receive Operation
Page 311 of 453
16. Clock Synchronous Serial Interface
2
C bus Interface Mode).

Related parts for R5F21272SNFP#U0