R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 42
R5F213J6CNNP#U0
Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet
1.R5F213J6CNNPU0.pdf
(750 pages)
Specifications of R5F213J6CNNP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
2.
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
Figure 2.1
b31
Central Processing Unit (CPU)
Note:
1. These registers comprise a register bank. There are two register banks.
CPU Registers
R2
R3
b15
IPL
b19
b19
INTBH
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b15
b15
b15
b15
R0H (high-order of R0)
R1H (high-order of R1)
b8
U
b7
PC
I
INTBL
USP
FLG
ISP
FB
SB
R2
R3
A1
b8b7
A0
O
R0L (low-order of R0)
R1L (low-order of R1)
B
S
Z
D
C
b0
b0
b0
b0
b0
b0
2. Central Processing Unit (CPU)
Frame base register
Address registers
Data registers
User stack pointer
Interrupt stack pointer
Static base register
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
Interrupt table register
Program counter
(1)
(1)
(1)
Page 11 of 715
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