R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 479
R5F213J6CNNP#U0
Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet
1.R5F213J6CNNPU0.pdf
(750 pages)
Specifications of R5F213J6CNNP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
Figure 23.2
Table 23.1
TXD2
RXD2
CLK2
CTS2
RTS2
SCL2
SDA2
Pin Name
RXD2
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in U2MR register
CLK1, CLK0, CKPOL, CRD, CRS: Bits in U2C0 register
U2ERE: Bit in U2C1 register
SP
SP
SP
P3_4, P3_7, or P6_6
P3_4, P3_7, or P4_5
P3_5
P3_3
P3_3
P3_4, P3_7, or P4_5
P3_4, P3_7, or P6_6
inversion circuit
1SP
STPS = 0
STPS = 1
2SP
STPS = 0
STPS = 1
1SP
2SP
RXD data
Block Diagram of UART2 Transmit/Receive Unit
Pin Configuration of UART2
0
SP
PAR
0
IOPOL = 0
IOPOL = 1
PAR
PAR
enabled
PRYE = 1
PRYE = 0
PAR
disabled
0
Assigned Pin
Not inverted
Inverted
PAR
disabled
PRYE = 0
PRYE = 1
PAR
enabled
SMD = 0
0
SMD = 1
UART
I
Clock
synchronous
type
2
C
UART
I
Clock
synchronous
type
2
C
0
0
UART
(9 bits)
I
2
C
0
UART
(9 bits)
I
UART
(7 bits)
UART
(8 bits)
Clock
synchronous type
2
C
D8
Clock
synchronous type
UART
(7 bits)
UART
(8 bits)
D8
I
Clock
synchronous type
UART
(8 bits)
UART
(9 bits)
2
I
Clock
synchronous
type
2
C
C
Output
Output
UART (7 bits)
Input
UART (7 bits)
Input
Logic inversion circuit + MSB/LSB conversion circuit
Logic inversion circuit + MSB/LSB conversion circuit
UART
(8 bits)
UART
(9 bits)
Data bus high-order bits
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Data bus low-order bits
I/O
I/O
I/O
I/O
U2ERE = 0
U2ERE = 1
Error signal output disabled
Error signal output enabled
Serial data output
Serial data input
Transfer clock I/O
Transmit control input
Receive control input
I
I
2
2
C mode clock I/O
C mode data I/O
Error signal
output
circuit
UART2 receive register
UART2 transmit register
IOPOL = 1
IOPOL = 0
23. Serial Interface (UART2)
Inverted
Function
Not inverted
TXD data
inversion
circuit
Page 448 of 715
U2TB
register
U2RB
register
TXD2
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