R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 570
R5F213J6CNNP#U0
Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet
1.R5F213J6CNNPU0.pdf
(750 pages)
Specifications of R5F213J6CNNP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
26.4
Figure 26.4
26.4.1
(1) I
(2) I
Legend:
S
SLA
R/W
A
DATA : Transmit/receive data
P
(a) I
(b) I
2
2
C bus format
C bus timing
When the FS bit in the SAR register is set to 0, the I
Figure 26.4 shows the I
8 bits.
: Start condition
: Slave address
: Indicates the direction of data transmission/reception
: Acknowledge
: Stop condition
2
2
C bus format (FS = 0)
C bus format When Start Condition is Retransmitted (FS = 0)
The master device changes the SDA signal from “H” to “L” while the SCL signal is held “H”.
Data is transmitted when:
R/W value is 1: From the slave device to the master device
R/W value is 0: From the master device to the slave device
The receive device sets the SDA signal to “L”.
The master device changes the SDA signal from “L” to “H” while the SCL signal is held “H”.
I
SDA
SCL
2
S
S
1
C bus Interface Mode
1
I
2
C bus Format
S
I
2
C bus Format and Bus Timing
SLA
SLA
7
7
1 to 7
SLA
1
1
R/W
R/W
8
2
1
R/W
1
C bus Format and Bus Timing. The first frame following the start condition consists of
A
A
1
1
9
A
DATA
DATA
n
n1
1 to 7
m1
DATA
8
A
1
m
A/A
1
2
9
C bus format is used for communication.
A
S
1
A/A
1 to 7
1
SLA
7
P
1
DATA
1
8
Upper: Number of transfer bits (n1, n2 = 1 to 8)
Lower: Number of transfer frames (m1, m2 = 1 or more)
Number of transfer bits (n = 1 to 8)
Number of transfer frames (m = 1 or more)
R/W
1
9
A
A
1
P
DATA
n2
26. I
m2
Page 539 of 715
2
C bus Interface
A/A
1
P
1
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