R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 606
R5F213J6CNNP#U0
Manufacturer Part Number
R5F213J6CNNP#U0
Description
MCU 1KB FLASH 32K ROM 36-QFN
Manufacturer
Renesas Electronics America
Series
R8C/3x/3JCr
Datasheet
1.R5F213J6CNNPU0.pdf
(750 pages)
Specifications of R5F213J6CNNP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
36-WQFN Exposed Pad, 36-HWQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
28. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling
amplifier. The analog input shares pins P0_1 to P0_4, P0_6, P0_7, and P1_0 to P1_3.
28.1
Table 28.1
Notes:
A/D conversion method
Analog input voltage
Operating clock φ AD
Resolution
Absolute accuracy
Operating mode
Analog input pin
A/D conversion start condition
Conversion rate per pin
( φ AD = fAD)
Table 28.1 lists the A/D Converter Performance. Figure 28.1 shows a Block Diagram of A/D Converter.
1. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh
2. Refer to Table 33.3 A/D Converter Characteristics for the operating clock φ A/D.
3. The conversion rate per pin is minimum 43 φ AD cycles for 8-bit and 10-bit resolution.
in 10-bit mode and FFh in 8-bit mode.
Overview
Item
A/D Converter Performance
(1)
(2)
Successive approximation (with capacitive coupling amplifier)
0 V to AVCC
fAD, fAD divided by 2, fAD divided by 4, fAD divided by 8
(fAD=f1 or fOCO-F)
8 bits or 10 bits selectable
AVCC = Vref = 5 V, φ AD = 20 MHz
AVCC = Vref = 3.3 V, φ AD = 16 MHz
AVCC = Vref = 3.0 V, φ AD = 10 MHz
AVCC = Vref = 2.2 V, φ AD = 5 MHz
One-shot mode, repeat mode 0, repeat mode 1, single sweep mode,
and repeat sweep mode
10 pins (AN0 to AN1, AN3 to AN6, and AN8 to AN11)
• Software trigger
• Timer RD
• Timer RC
• External trigger
Minimum 43 φ AD cycles
(Refer to 28.3.3 A/D Conversion Start Condition .)
• 8-bit resolution
• 10-bit resolution ±3 LSB
• 8-bit resolution
• 10-bit resolution ±5 LSB
• 8-bit resolution
• 10-bit resolution ±5 LSB
• 8-bit resolution
• 10-bit resolution ±5 LSB
±2 LSB
±2 LSB
±2 LSB
±2 LSB
Performance
28. A/D Converter
Page 575 of 715
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