R5F213J6CNNP#U0 Renesas Electronics America, R5F213J6CNNP#U0 Datasheet - Page 659

• Manufacturer Part Number: R5F213J6CNNP#U0
• Description: MCU 1KB FLASH 32K ROM 36-QFN
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/3JCr

Specifications of R5F213J6CNNP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-WQFN Exposed Pad, 36-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/3JC Group
REJ09B0602-0100 Rev.1.00
May 12, 2010
31.4.11 Software Commands
Table 31.5
WA: Write address
WD: Write data
BA: Any block address
BT: Starting block address
×:
Read array
Clear status register
Program
Block erase
Lock bit program
Read lock bit status
Block blank check
31.4.11.1 Read Array Command
31.4.11.2 Clear Status Register Command
The software commands are described below. Read or write commands and data in 8-bit units.
Do not input any command other than those listed in the table below.
The read array command is used to read the flash memory.
When FFh is written in the first bus cycle, the MCU enters read array mode. When the read address is input in
the following bus cycles, the content of the specified address can be read in 8-bit units.
Since read array mode remains until another command is written, the contents of multiple addresses can be read
continuously.
In addition, after a reset, the MCU enters read array mode after a program, block erase, block blank check, read
lock bit status, or clear status register command, or after entering erase-suspend.
The clear status register command is used to set bits FST4 and FST5 in the FST register to 0.
When 50h is written in the first bus cycle, bits FST4 and FST5 in the FST register are set to 0.
Any address in the user ROM area
Command
Software Commands
Mode
Write
Write
Write
Write
Write
Write
Write
First Bus Cycle
Address
WA
BT
×
×
×
×
×
Data
FFh
50h
40h
20h
77h
71h
25h
Mode
Write
Write
Write
Write
Write
Second Bus Cycle
Address
WA
BA
BT
BT
BA
31. Flash Memory
Page 628 of 715
Data
D0h
D0h
D0h
D0h
WD